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公开(公告)号：US09755506B2
公开(公告)日：2017-09-05
申请号：US14566944
申请日：2014-12-11
发明人： Leland Chang , Robert K. Montoye , Jae-sun Seo , Albert M. Young
摘要： An apparatus for providing on-chip voltage-regulated power includes a switched capacitor voltage conversion circuit that receives an elevated power demand signal and operates at a base rate when the elevated power demand signal is not active and at an elevated rate when the elevated power demand signal is active. The switched capacitor voltage conversion circuit comprises an auxiliary set of transistors that are disabled, when the elevated power demand signal is not active and enabled, when the elevated power demand signal is active. The apparatus may also include a droop detection circuit that monitors a monitored power signal and activates the elevated power demand signal in response to the monitored power signal dropping below a selected voltage level. The monitored power signal may be a voltage input provided by an input power supply for the switched capacitor voltage conversion circuit. A corresponding method is also disclosed herein.
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公开(公告)号：US11915966B2
公开(公告)日：2024-02-27
申请号：US17342650
申请日：2021-06-09
发明人： Ruilong Xie , Takeshi Nogami , Roy R. Yu , Balasubramanian Pranatharthiharan , Albert M. Young , Kisik Choi , Brent Anderson
IPC分类号： H01L21/74 , H01L21/768 , H01L23/528 , H01L23/535 , H01L27/088
CPC分类号： H01L21/743 , H01L21/76805 , H01L23/5286 , H01L23/535 , H01L27/0886
摘要： A method of manufacturing a semiconductor device is provided. The method includes forming a first trench partially through a first substrate from a first side of the first substrate. The method also includes widening a bottom portion of the first trench to form a lateral footing area of the first trench. The method includes forming a first metallization in the first trench; forming a second trench through a second substrate from a second side of the second substrate to expose at least a portion of first metallization in an area corresponding to the lateral footing area of the first trench, the second side being opposite to the first side. The method also includes forming a second metallization in the second trench in contact with the first metallization.
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公开(公告)号：US20240014135A1
公开(公告)日：2024-01-11
申请号：US17860082
申请日：2022-07-07
发明人： Junli Wang , Albert M. Chu , Albert M. Young , Chen Zhang , Su Chen Fan , Ruilong Xie
IPC分类号： H01L23/528 , H01L23/48 , H01L21/8234 , H01L29/786
CPC分类号： H01L23/5286 , H01L23/481 , H01L21/823475 , H01L29/78696
摘要： A semiconductor device including a first source/drain region (S/D) located on a frontside of a substrate, wherein the first source/drain region has a first width, a second S/D region located on the frontside of the substrate, wherein the second source/drain region is located above the first source drain region, wherein the second source/drain region has second width, wherein the first width is larger than the second width, a first power rail located on a backside of the substrate, a second power rail located on the backside of the substrate, a first connector in contact with the first source/drain region, wherein the first connector is only in contact with a sidewall of the first source/drain region, and a second connector in contact with the second source/drain region, wherein the second connector is in contact with a top surface and a side surface of the second source/drain region.
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公开(公告)号：US20230420502A1
公开(公告)日：2023-12-28
申请号：US17808124
申请日：2022-06-22
发明人： Heng Wu , Junli Wang , Ruilong Xie , Albert M. Young , Albert M. Chu , Brent A. Anderson , Ravikumar Ramachandran
IPC分类号： H01L29/06 , H01L29/786 , H01L29/775 , H01L29/66 , H01L21/8234
CPC分类号： H01L29/0673 , H01L29/78618 , H01L29/78696 , H01L29/775 , H01L29/66439 , H01L21/823412 , H01L21/823418
摘要： A field effect transistor (“FET”) stack, including a lower FET, and an upper FET, a first contact to a lower source drain of the lower FET, a first silicide between the first contact and the lower source drain, the first contact is adjacent to a vertical side surface of the lower source drain, a first overlap region between the first silicide and the first contact is less than a second overlap region between the first silicide and the first source drain. The first contact has a reverse tapper metal stud profile. Forming a first contact to a lower source drain of a lower FET of an FET stack, forming a first silicide between the first contact and the lower source drain, the first contact is adjacent to a vertical side surface of the lower source drain.
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公开(公告)号：US20230420303A1
公开(公告)日：2023-12-28
申请号：US17846423
申请日：2022-06-22
发明人： Albert M. Young , Albert M. Chu , Junli Wang
IPC分类号： H01L21/8238 , H01L23/528 , H01L23/48 , H01L23/522 , H01L25/065 , H01L27/06
CPC分类号： H01L21/823807 , H01L21/823871 , H01L23/5286 , H01L27/0688 , H01L23/5226 , H01L25/0657 , H01L23/481
摘要： A semiconductor structure including a reliable power rail in stacked field effect transistor technology with unequal device footprints is provided that mitigates, and in some cases even eliminates, shorting risks that are typically associated using long bars in advanced logic applications.
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公开(公告)号：US20230360971A1
公开(公告)日：2023-11-09
申请号：US17662436
申请日：2022-05-09
发明人： Heng Wu , Ruilong Xie , Albert M. Chu , Albert M. Young , Junli Wang , Brent A. Anderson
IPC分类号： H01L21/768 , H01L23/48 , H01L29/417
CPC分类号： H01L21/76895 , H01L23/481 , H01L21/76897 , H01L29/41775 , H01L24/32
摘要： Embodiments of present invention provide a transistor structure. The transistor structure includes a first and a second transistor in a first transistor layer; a first and a second transistor in a second transistor layer, respectively, above the first and the second transistor in the first transistor layer; a metal routing layer between the first transistor layer and the second transistor layer; a first local interconnect connecting the first transistor of the first transistor layer to the metal routing layer; and a second local interconnect connecting the metal routing layer to the second transistor of the second transistor layer. A method of manufacturing the transistor structure is also provided.
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公开(公告)号：US20230217639A1
公开(公告)日：2023-07-06
申请号：US18183276
申请日：2023-03-14
发明人： Tsung-Sheng Kang , Ardasheir Rahman , Tao Li , Albert M. Young
IPC分类号： H01L29/66 , H01L29/78 , H01L23/528 , H01L27/092
CPC分类号： H10B10/12 , H01L29/7827 , H01L23/5286 , H01L27/092
摘要： A memory device includes a first field effect transistor (FET) stack on a first bottom source/drain region, which includes a first vertical transport field effect transistor (VTFET) device between a second VTFET device and the first source/drain region, and a second FET stack on a second bottom source/drain region, which includes a third VTFET device between a fourth VTFET device and the bottom source/drain region. The memory device includes a third FET stack on a third bottom source/drain region, which includes a fifth VTFET between a sixth VTFET and the third source/drain region, which is laterally adjacent to the first and second source/drain regions. The memory device includes a first electrical connection interconnecting a gate structure of the third VTFET with a gate structure of the fifth VTFET, and a second electrical connection interconnecting a gate structure of the second VTFET with a gate structure of the sixth VTFET.
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公开(公告)号：US20240194601A1
公开(公告)日：2024-06-13
申请号：US18062624
申请日：2022-12-07
发明人： Albert M. Chu , Nicholas Anthony Lanzillo , Albert M. Young , Junli Wang , Brent A. Anderson , Ruilong Xie , Lawrence A. Clevenger , REINALDO VEGA
IPC分类号： H01L23/528 , G06F30/392 , G06F30/394 , H01L23/522 , H01L27/092
CPC分类号： H01L23/5286 , G06F30/392 , G06F30/394 , H01L23/5226 , H01L27/0922
摘要： A semiconductor structure is presented having a plurality of circuit rows, a plurality of first power rails positioned on front sides of the plurality of circuit rows, a plurality of second power rails positioned on back sides of the plurality of circuit rows, and power tap cells associated with each the plurality of circuit rows, wherein each of the power tap cells includes one or more power vias connecting at least one first power rail of the plurality of first power rails to at least one second power rail of the plurality the second power rails. In one instance, the plurality of second power rails are orthogonal to the plurality of first power rails. in another instance, the plurality of first power rails are horizontally offset from the plurality of second power rails. The one or more power vias include at least two or more different sized power vias.
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公开(公告)号：US20240164089A1
公开(公告)日：2024-05-16
申请号：US18054161
申请日：2022-11-10
发明人： Albert M. Chu , Junli Wang , Albert M. Young , Brent A. Anderson , Ruilong Xie , Carl Radens
IPC分类号： H01L27/112
CPC分类号： H01L27/11206
摘要： Embodiments of the present invention are directed to processing methods and resulting structures having backside programmable memory cells. In a non-limiting embodiment, a front end of line structure having a plurality of programmable cells is formed such that each programmable cell includes a backside via in direct contact with a device region of the respective cell. A first portion of the backside vias defines one or more placeholder backside vias and a second portion defines one or more programmed backside vias. A back end of line structure (word line) is formed on a first surface of the front end of line structure. A backside structure is formed on a second surface of the front end of line structure opposite the first surface. The backside structure includes a backside metallization layer (bit line) in direct contact with the one or more programmed backside vias.
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公开(公告)号：US20240162231A1
公开(公告)日：2024-05-16
申请号：US18054160
申请日：2022-11-10
发明人： Albert M. Chu , Brent A. Anderson , Junli Wang , Albert M. Young , Ruilong Xie , Carl Radens
IPC分类号： H01L27/118
CPC分类号： H01L27/11807 , H01L2027/11875 , H01L2027/11881
摘要： Embodiments of the present invention are directed to processing methods and resulting structures for integrated circuits having backside programmable gate arrays. In a non-limiting embodiment, a front end of line structure having an array of transistors is formed such that each transistor of the array of transistors includes one or more placeholder backside vias. A first portion of the backside vias defines one or more placeholder backside vias and a second portion of the one or more backside vias defines one or more programmed backside vias. A back end of line structure is formed on a first surface of the front end of line structure. A backside structure is formed on a second surface of the front end of line structure opposite the first surface. The backside structure includes a backside metallization layer in direct contact with the one or more programmed backside vias.
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