Abstract:
A bipolar silicon transistor includes at least one emitter zone with n.sup.+ arsenic doping and with a phosphorus doping. The ratio between arsenic dopant concentration and phosphorus dopant concentration is between 10:1 and 500:1 in the at least one emitter zone. The at least one emitter zone may also have a penetration depth of less than 0.5 .mu.m. A method for producing a bipolar silicon transistor includes implanting a n.sup.+ -doped emitter zone with arsenic, implanting the n.sup.+ -doped emitter zone with phosphorus, setting a ratio in the n.sup.+ -doped emitter zone between the arsenic dopant concentration and phosphorus dopant concentration to between 10:1 and 500:1, and annealing crystal defects.
Abstract:
Metal is melted in an induction-heated crucible (13) on which a mold (10) with a downward-facing filling opening (26) is located in the melting position. After melting the metal, the crucible (13) and the mold (10) are jointly rotated about a horizontal axis (A--A) into a tilting position in which the molten material flows from the crucible (13) into the mold (10). In order to melt reactive metals, melting is done in a crucible (13) that is surrounded by a vacuum, this crucible being surrounded by an induction coil (15) outside of the vacuum. The mold (10) is located in a vacuum-sealed casting chamber (6) which is evacuated together with the crucible (13) prior to melting and casting is carried out by a joint tilting of the crucible (13), casting chamber (6) and mold (10) by at least 180 degrees while the vacuum is maintained.
Abstract:
A high-frequency transistor has a suitably doped and structured semiconductor chip (1) that is composed of a doped Si substrate and has base, collector and emitter contactings (2, 3, 4). The chip (1) is surrounded by a housing (8), the contacts being connected to the respective base, collector and emitter terminals (6, 7, 5) of the housing. With the housing the transistor has a high gain at frequencies above 1 GHz. The base, collector and emitter contacts (2, 3, 4) are provided at the upper side of the semiconductor chip (1). The semiconductor chip (1) has its underside arranged on the emitter terminal (5) of the housing (8) which is fashioned as HF ground. The emitter contact (4) is connected over a short distance to the emitter terminal (5) of the housing (8). The base and collector contacts (2, 3) are each respectively connected via at least one bond wire (9) to the respective base or collector terminals (6, 7).
Abstract:
A process controlling a thermal installation is described. The flow of a process liquid through a heat exchanger is achieved dependent upon two temperatures. One is the return temperature of the process liquid which, through the switching on and off or modulation of a circulation pump is maintained at a constant value. The other is the room or outside temperatures or the difference between these two temperatures, whereby during the deviation of a predeterminable limiting value the pump is also switched on and off or modulated. Since the supply temperature from a boiler has a constant temperature, for a central heating system the same amount of heat is drawn from each unit of heating water and thus the measure of the pump flow is sufficient to determine the actual heat consumption. Thereby the fair division of heating costs for each tenant according to actual amount consumed is made possible.
Abstract:
A chain amplifier assembly, includes a semiconductor body, a chain amplifier disposed in the semiconductor body and having an input, an output, a plurality of interconnected amplifier stages having transition regions therebetween, each of the stages including a plurality of field-effect transistors having source, gate and drain terminals, each of the source terminals being connected to a given common source potential, a plurality of ohmic resistors and inductances connected in series between the gate terminals forming a gate line, a plurality of capacitances each having a lead connected in parallel to the gate line and another lead connected to the given common source potential, a plurality of inductances connected in series between the drain terminals forming a drain line, a plurality of additional ohmic resistors having a lead connected in parallel to the drain line and another lead connected to the given common source potential, a plurality of additional capacitances having a lead connected in parallel to the drain line and another lead connected to the given common source potential, matching elements in the form of capacitances, inductances and ohmic resistors connected at the input, output and transition regions, the drain and gate lines being wave guides formed with metal coatings, insulating coatings and doping concentrations required for the field-effect transistors, and additional circuit elements monolithically integrated into the semiconductor body.
Abstract:
A transistor assembly having a transistor includes a plurality of transistor regions, each of which has a vertical transistor structure having a collector semiconductor region, a base semiconductor region and an emitter semiconductor region, emitter contacting regions arranged above the transistor regions and base contacting regions connected to the base semiconductor regions via a polycrystalline semiconductor layer, wherein the polycrystalline semiconductor layer is structured such that the base contacting regions of transistor regions which are not part of the transistor are electrically isolated from base contacting regions of transistor regions which are part of the transistor.
Abstract:
A semiconductor structure including a substrate, a device layer and a contact arranged on the substrate, comprises an ESD protective means, arranged between the substrate and the contact, such, that in the ESD case a breakthrough from the ESD protective means to the contact occurs.
Abstract:
A method for producing a contact structure on a structured surface comprising producing a first conductive layer on the structured surface, wherein the first conductive layer comprising tungsten. A conductive seed layer is produced on the first conductive layer, the contact structure being produced by electroplating on the seed layer. The first conductive layer serves as an etch stop for selectively removing substrate material from the backside.
Abstract:
A gasification reactor comprising of a slow turning rotation chamber (1) with tapered end pieces (7) and sealed by stationary closures (8, 9). The chamber is divided by rings (3, 3') into three sections (4, 5, 6). The first section (4) is used to dry and pre-heat the combustible material (12). Section (5) is the gasification zone and section (6) is used to collect and transport the ash to the outside of the chamber. In order to obtain a better insulation against loss of heat an inner cylinder (24) is fitted into the chamber. The feed stock material (12) is brought into the chamber with a hollow piston (13) through the stationary closure (8) and inside the chamber the material is moved along by the rotation of the chamber. Fresh air supply is introduced into the chamber through special form parts (25), and the combustible gas is collected and returned to the outside with the pipe (31). Ash and slag are lifted and deposited in a collector (21) from where they are brought to the outside. A continuous operation is possible, and the gasification process can be pressurized to supply the gas directly to a user without the need for a gas compressor. Almost any solid combustible material can be gasified such as wood, paper, coal in small grain size, plastic, and dry biomass. Small amounts of waste oil can be mixed with the feed stock.
Abstract:
In a monolithically integratable microwave attenuation element, the attenuation is switchable between various, discrete values and the signal experiences only a small phase shift when switched between the individual attenuation values. The drain-source paths of field effect transistors (Q1, Q2, Q3) in the attenuation element are arranged in a PI configuration. Resistors (R11, R22, R33) are connected parallel to the drain-source paths of the field effect transistors (Q1, Q2, Q3) that are arranged in PI configuration.