公开(公告)号：US20160086851A1

公开(公告)日：2016-03-24

申请号：US14490598

申请日：2014-09-18

申请人： Jungrae Park ,  Wei-Sheng Lei ,  James S. Papanu ,  Brad Eaton ,  Ajay Kumar

发明人： Jungrae Park ,  Wei-Sheng Lei ,  James S. Papanu ,  Brad Eaton ,  Ajay Kumar

IPC分类号： H01L21/78 ,  B23K26/36 ,  H01L21/67 ,  H01J37/32 ,  H01L21/308 ,  H01L21/3065

CPC分类号： H01L21/78 ,  B23K26/364 ,  H01J37/32889 ,  H01J2237/335 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/67207

摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with an adaptive optics-controlled laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

摘要翻译： 对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。 在一个例子中，对具有多个集成电路的半导体晶片进行切割的方法包括在半导体晶片上形成掩模，该掩模由覆盖并保护集成电路的层组成。 然后用自适应光学控制激光划线工艺对掩模进行构图，以提供具有间隙的图案化掩模，暴露集成电路之间的半导体晶片的区域。 然后通过图案化掩模中的间隙对半导体晶片进行等离子体蚀刻，以对集成电路进行分离。

公开(公告)号：US09012305B1

公开(公告)日：2015-04-21

申请号：US14167347

申请日：2014-01-29

申请人： Wei-Sheng Lei ,  Jungrae Park ,  James S. Papanu ,  Brad Eaton ,  Ajay Kumar

发明人： Wei-Sheng Lei ,  Jungrae Park ,  James S. Papanu ,  Brad Eaton ,  Ajay Kumar

IPC分类号： H01L21/78 ,  H01L21/82 ,  H01L21/67 ,  H01L21/3065

CPC分类号： H01L21/3065 ,  H01L21/02057 ,  H01L21/30655 ,  H01L21/3081 ,  H01L21/31105 ,  H01L21/32131 ,  H01L21/67207 ,  H01L21/78

摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask is patterned with a laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. Subsequent to patterning the mask, the exposed regions of the semiconductor wafer are cleaned with an anisotropic plasma process non-reactive to the exposed regions of the semiconductor wafer. Subsequent to cleaning the exposed regions of the semiconductor wafer, the semiconductor wafer is plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

摘要翻译： 对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。 在一个示例中，对具有多个集成电路的半导体晶片进行切割的方法包括在半导体晶片上形成掩模，该掩模包括覆盖并保护集成电路的层。 通过激光划线工艺对掩模进行构图，以提供具有间隙的图案化掩模，暴露半导体晶片在集成电路之间的区域。 在图案化掩模之后，用与半导体晶片的暴露区域无反应的各向异性等离子体处理来清洁半导体晶片的暴露区域。 在清洁半导体晶片的暴露区域之后，通过图案化掩模中的间隙对半导体晶片进行等离子体蚀刻，以对集成电路进行分离。

公开(公告)号：US09601375B2

公开(公告)日：2017-03-21

申请号：US14697391

申请日：2015-04-27

申请人： Wei-Sheng Lei ,  Brad Eaton ,  Jungrae Park ,  Ajay Kumar ,  James S. Papanu ,  Prabhat Kumar

发明人： Wei-Sheng Lei ,  Brad Eaton ,  Jungrae Park ,  Ajay Kumar ,  James S. Papanu ,  Prabhat Kumar

IPC分类号： H01L21/301 ,  H01L21/46 ,  H01L21/78 ,  H01L21/447 ,  H01L21/48 ,  H01L21/50 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/268 ,  H01L21/67 ,  H01L21/683

CPC分类号： H01L21/78 ,  H01L21/268 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/67069 ,  H01L21/67207 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381

摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits on a front side of the semiconductor wafer includes adhering a back side the semiconductor wafer on the dicing tape of a substrate carrier. Subsequent to adhering the semiconductor wafer on a dicing tape, the dicing tape is treated with a UV-cure process. Subsequent to treating the dicing tape with the UV-cure process, a dicing mask is formed on the front side of the semiconductor wafer, the dicing mask covering and protecting the integrated circuits. The dicing mask is patterned with a laser scribing process to provide gaps in the dicing mask, the gaps exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is plasma etched through the gaps in the dicing mask layer to singulate the integrated circuits.

公开(公告)号：US09299611B2

公开(公告)日：2016-03-29

申请号：US14167300

申请日：2014-01-29

申请人： Wei-Sheng Lei ,  Brad Eaton ,  Ajay Kumar ,  James S. Papanu ,  Jungrae Park

发明人： Wei-Sheng Lei ,  Brad Eaton ,  Ajay Kumar ,  James S. Papanu ,  Jungrae Park

IPC分类号： H01L31/06 ,  H01L21/78 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/67 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/311

CPC分类号： H01L21/78 ,  B23K26/361 ,  B23K2103/172 ,  B23K2103/50 ,  H01L21/0273 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31058 ,  H01L21/31127 ,  H01L21/67207

摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask is exposed to a plasma treatment process to increase an etch resistance of the mask. The mask is patterned with a laser scribing process to provide gaps in the mask, the gaps exposing regions of the semiconductor wafer between the integrated circuits. Subsequent to exposing the mask to the plasma treatment process, the semiconductor wafer is plasma etched through the gaps in the mask to singulate the integrated circuits.

摘要翻译： 对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。 在一个示例中，对具有多个集成电路的半导体晶片进行切割的方法包括在半导体晶片上形成掩模，该掩模包括覆盖并保护集成电路的层。 将掩模暴露于等离子体处理工艺以增加掩模的耐蚀刻性。 用激光划线工艺对掩模进行图案化，以在掩模中提供间隙，使间隙暴露集成电路之间的半导体晶片的区域。 在将掩模暴露于等离子体处理工艺之后，通过掩模中的间隙对半导体晶片进行等离子体蚀刻，以对集成电路进行分离。

公开(公告)号：US20150287638A1

公开(公告)日：2015-10-08

申请号：US14248205

申请日：2014-04-08

申请人： Jungrae Park ,  Wei-Sheng Lei ,  James S. Papanu ,  Brad Eaton ,  Ajay Kumar

发明人： Jungrae Park ,  Wei-Sheng Lei ,  James S. Papanu ,  Brad Eaton ,  Ajay Kumar

IPC分类号： H01L21/78 ,  B23K26/36

CPC分类号： H01L21/78 ,  B23K26/364 ,  B23K26/402 ,  H01L21/02057 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/3081 ,  H01L21/31105 ,  H01L21/31127 ,  H01L21/32131 ,  H01L21/76224

摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a collimated laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

摘要翻译： 对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。 在一个例子中，对具有多个集成电路的半导体晶片进行切割的方法包括在半导体晶片上形成掩模，该掩模由覆盖并保护集成电路的层组成。 然后用准直激光划线工艺对掩模进行构图，以提供具有间隙的图案化掩模，暴露集成电路之间的半导体晶片的区域。 然后通过图案化掩模中的间隙对半导体晶片进行等离子体蚀刻，以对集成电路进行分离。

公开(公告)号：US20150221505A1

公开(公告)日：2015-08-06

申请号：US14658102

申请日：2015-03-13

申请人： Jungrae Park ,  Wei-Sheng Lei ,  Prabhat Kumar ,  James S. Papanu ,  Brad Eaton ,  Ajay Kumar

发明人： Jungrae Park ,  Wei-Sheng Lei ,  Prabhat Kumar ,  James S. Papanu ,  Brad Eaton ,  Ajay Kumar

IPC分类号： H01L21/02 ,  H01L21/683 ,  H01L21/308 ,  B05B3/10 ,  B05B1/00

CPC分类号： H01L21/02282 ,  B05B1/00 ,  B05B3/1014 ,  B05B3/1035 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/6715 ,  H01L21/6835 ,  H01L21/78 ,  H01L2221/68327

摘要： Improved wafer coating processes, apparatuses, and systems are described. In one embodiment, an improved spin-coating process and system is used to form a mask for dicing a semiconductor wafer with a laser plasma dicing process. In one embodiment, a spin-coating apparatus for forming a film over a semiconductor wafer includes a rotatable stage configured to support the semiconductor wafer. The rotatable stage has a downward sloping region positioned beyond a perimeter of the semiconductor wafer. The apparatus includes a nozzle positioned above the rotatable stage and configured to dispense a liquid over the semiconductor wafer. The apparatus also includes a motor configured to rotate the rotatable stage.

摘要翻译： 描述了改进的晶片涂布工艺，装置和系统。 在一个实施例中，改进的旋涂工艺和系统用于形成用激光等离子体切割工艺切割半导体晶片的掩模。 在一个实施例中，用于在半导体晶片上形成膜的旋涂装置包括被配置为支撑半导体晶片的可旋转台。 可旋转台具有位于半导体晶片周边之外的向下倾斜区域。 该设备包括位于可旋转台上方并被配置为在半导体晶片上分配液体的喷嘴。 该装置还包括构造成旋转可旋转台的马达。

公开(公告)号：US09159624B1

公开(公告)日：2015-10-13

申请号：US14589913

申请日：2015-01-05

申请人： Wei-Sheng Lei ,  Prabhat Kumar ,  James S. Papanu ,  Brad Eaton ,  Ajay Kumar

发明人： Wei-Sheng Lei ,  Prabhat Kumar ,  James S. Papanu ,  Brad Eaton ,  Ajay Kumar

IPC分类号： H01L21/78 ,  H01L21/8234

CPC分类号： H01L21/78 ,  H01L21/6836 ,  H01L21/8234 ,  H01L2221/68327 ,  H01L2221/6834

摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves laminating a polymeric mask layer onto a front side of the semiconductor wafer by dry film vacuum lamination, the polymeric mask layer covering and protecting the integrated circuits. The method also involves patterning the polymeric mask layer with a laser scribing process to provide gaps in the polymeric mask layer, the gaps exposing regions of the semiconductor wafer between the integrated circuits. The method also involves plasma etching the semiconductor wafer through the gaps in the polymeric mask layer to singulate the integrated circuits. The method also involves, subsequent to plasma etching the semiconductor wafer, removing the polymeric mask layer.

摘要翻译： 对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。 在一个实例中，对具有多个集成电路的半导体晶片进行切割的方法包括通过干膜真空层压将聚合物掩模层层压到半导体晶片的正面上，该聚合物掩模层覆盖并保护集成电路。 该方法还包括用激光划线工艺图案化聚合物掩模层，以在聚合物掩模层中提供间隙，间隙暴露集成电路之间的半导体晶片的区域。 该方法还包括通过聚合物掩模层中的间隙等离子体蚀刻半导体晶片以对集成电路进行分离。 该方法还涉及在等离子体蚀刻半导体晶片之后，去除聚合物掩模层。

公开(公告)号：US08912078B1

公开(公告)日：2014-12-16

申请号：US14254632

申请日：2014-04-16

申请人： Wei-Sheng Lei ,  James S. Papanu ,  Aparna Iyer ,  Brad Eaton ,  Ajay Kumar

发明人： Wei-Sheng Lei ,  James S. Papanu ,  Aparna Iyer ,  Brad Eaton ,  Ajay Kumar

IPC分类号： H01L21/00 ,  H01L21/78 ,  H01L21/683

CPC分类号： H01L21/78 ,  H01L21/268 ,  H01L21/3065 ,  H01L21/6836 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/12041 ,  H01L2224/11 ,  H01L2924/00

摘要： Approaches for hybrid laser scribe and plasma etch dicing process for a wafer having backside solder bumps are described. For example, a method of dicing a semiconductor wafer having integrated circuits on a front side thereof and corresponding arrays of metal bumps on a backside thereof involves applying a dicing tape to the backside of the semiconductor wafer, the dicing tape covering the arrays of metal bumps. The method also involves, subsequently, forming a mask on the front side of the semiconductor wafer, the mask covering the integrated circuits. The method also involves forming scribe lines on the front side of the semiconductor wafer with a laser scribing process, the scribe lines formed in the mask and between the integrated circuits. The method also involves plasma etching the semiconductor wafer through the scribe lines to singulate the integrated circuits, the mask protecting the integrated circuits during the plasma etching.

摘要翻译： 描述了具有背面焊料凸块的晶片的混合激光划片和等离子体蚀刻切割工艺的方法。 例如，在其前侧具有集成电路的半导体晶片的切割方法和背面的金属凸块的相应阵列包括在半导体晶片的背面施加切割带，该切割带覆盖金属凸块的阵列 。 该方法还包括在半导体晶片的正面上形成掩模，该掩模覆盖集成电路。 该方法还涉及通过激光划线工艺在半导体晶片的正面上形成刻划线，在掩模中形成划线并在集成电路之间。 该方法还包括通过划线等离子体蚀刻半导体晶片以对集成电路进行分离，掩模在等离子体蚀刻期间保护集成电路。

公开(公告)号：US09209084B2

公开(公告)日：2015-12-08

申请号：US14454656

申请日：2014-08-07

申请人： Wei-Sheng Lei ,  Brad Eaton ,  James S. Papanu ,  Ajay Kumar

发明人： Wei-Sheng Lei ,  Brad Eaton ,  James S. Papanu ,  Ajay Kumar

IPC分类号： H01L21/00 ,  H01L21/78 ,  H01L21/3065 ,  H01L21/82 ,  B23K26/00 ,  B23K26/06

CPC分类号： H01L21/78 ,  B23K26/0006 ,  B23K26/0624 ,  B23K26/50 ,  B23K26/53 ,  B23K26/57 ,  B23K2101/40 ,  B23K2103/56 ,  H01L21/3065 ,  H01L21/82

摘要： Maskless hybrid laser scribing and plasma etching wafer dicing processes are described. In an example, a method of dicing a semiconductor wafer having a front surface with a plurality of integrated circuits thereon and having a passivation layer disposed between and covering metal pillar/solder bump pairs of the integrated circuits involves laser scribing, without the use of a mask layer, the passivation layer to provide scribe lines exposing the semiconductor wafer. The method also involves plasma etching the semiconductor wafer through the scribe lines to singulate the integrated circuits, wherein the passivation layer protects the integrated circuits during at least a portion of the plasma etching. The method also involves thinning the passivation layer to partially expose the metal pillar/solder bump pairs of the integrated circuits.

公开(公告)号：US20150279739A1

公开(公告)日：2015-10-01

申请号：US14226038

申请日：2014-03-26

申请人： Wei-Sheng Lei ,  James S. Papanu ,  Aparna Iyer ,  Brad Eaton ,  Ajay Kumar

发明人： Wei-Sheng Lei ,  James S. Papanu ,  Aparna Iyer ,  Brad Eaton ,  Ajay Kumar

IPC分类号： H01L21/78 ,  H01L23/544

CPC分类号： H01L21/78 ,  H01L21/3065 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/544 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2224/11 ,  H01L2224/16145 ,  H01L2224/16225

摘要： Approaches for front side laser scribe plus backside bump formation and laser scribe and plasma etch dicing process are described. For example, a method of dicing a semiconductor wafer having integrated circuits on a front side thereof involves forming first scribe lines on the front side, between the integrated circuits, with a first laser scribing process. The method also involves forming arrays of metal bumps on a backside of the semiconductor wafer, each array corresponding to one of the integrated circuits. The method also involves forming second scribe lines on the backside, between the arrays of metal bumps, with a second laser scribing process, wherein the second scribe lines are aligned with the first scribe lines. The method also involves plasma etching the semiconductor wafer through the second scribe lines to singulate the integrated circuits.

摘要翻译： 描述了用于前侧激光划片加背面凸块形成和激光划线和等离子体蚀刻切割工艺的方法。 例如，在前侧具有集成电路的半导体晶片的切割方法包括在第一激光划线工序之间，在集成电路之间的正面侧形成第一划线。 该方法还涉及在半导体晶片的背面形成金属凸块阵列，每​​个阵列对应于一个集成电路。 该方法还涉及在金属凸块阵列之间的背侧，第二激光划线工艺之间形成第二刻划线，其中第二刻划线与第一划刻线对准。 该方法还包括通过第二划线等离子体蚀刻半导体晶片以对集成电路进行分离。