-
11.发明授权
公开(公告)号：US5262989A
公开(公告)日：1993-11-16
申请号：US760187
申请日：1991-09-16
Applicant: Young-Taek Lee , Jin-Man Han , Kyoung-Ho Kim , Hong-Seon Hwang
Inventor： Young-Taek Lee , Jin-Man Han , Kyoung-Ho Kim , Hong-Seon Hwang
Abstract: A back-bias level sensor used for a semiconductor device wherein a sensing current for sensing a back-bias voltage is prevented from directly flowing into the substrate (or the back-bias voltage terminal). The gate of a PMOS transistor is provided with the back-bias voltage while the source is provided with a ground voltage, so that a pump circuit performs the pumping operation to increase the back-bias voltage when the back-bias voltage is lower than a predetermined voltage level; otherwise, the pump circuit is de-energized, thereby reducing the back-bias voltage.
Abstract translation: 用于半导体器件的背偏置电平传感器，其中防止用于感测反偏压的感测电流直接流入衬底（或背偏电压端）。 PMOS晶体管的栅极被提供有反向偏置电压，同时源极具有接地电压，使得泵电路进行泵浦操作以在背偏电压低于 预定电压电平; 否则，泵电路被断电，从而减小背偏电压。
-
公开(公告)号：US09147492B2
公开(公告)日：2015-09-29
申请号：US14546477
申请日：2014-11-18
Applicant: Sunil Shim , Jin-Man Han , Sang-Wan Nam , Won-Taeck Jung
Inventor： Sunil Shim , Jin-Man Han , Sang-Wan Nam , Won-Taeck Jung
IPC: G11C16/00 , G11C16/34 , G11C16/10 , G11C16/16 , H01L27/115 , H01L29/792 , G11C16/14
CPC classification number: G11C16/3418 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/349 , H01L27/11578 , H01L27/11582 , H01L29/7926
Abstract: According to example embodiments, a control method of a nonvolatile memory device, which includes a plurality of memory blocks on a substrate, each memory block including a plurality of sub blocks stacked in a direction perpendicular to the substrate and being configured to be erased independently and each sub block including a plurality of memory cells stacked in the direction perpendicular to the substrate. The control method includes comparing a count value of a first memory block with a reference value, the count value determined according to the number of program, read, or erase operations executed at the first memory block after data is programmed in the first memory block; and if the count value is greater than or equal to the reference value, performing a reprogram operation in which data programmed in first the memory block is read and the read data is programmed in a second memory block.
Abstract translation: 根据示例性实施例，一种非易失性存储器件的控制方法，其包括在衬底上的多个存储块，每个存储块包括沿垂直于衬底的方向堆叠的多个子块，并且被配置为独立擦除， 每个子块包括在垂直于衬底的方向上堆叠的多个存储单元。 控制方法包括将第一存储块的计数值与参考值进行比较，所述计数值根据在第一存储器块中的数据被编程之后在第一存储器块执行的程序，读取或擦除操作的数量确定; 并且如果所述计数值大于或等于所述参考值，则执行重新编程操作，其中在第一存储器块中编程的数据被读取并且所读取的数据被编程在第二存储器块中。
-
公开(公告)号：US08174889B2
公开(公告)日：2012-05-08
申请号：US12703901
申请日：2010-02-11
Applicant: Dzung H. Nguyen , Benjamin Louie , Hagop A. Nazarian , Aaron Yip , Jin-Man Han
Inventor： Dzung H. Nguyen , Benjamin Louie , Hagop A. Nazarian , Aaron Yip , Jin-Man Han
IPC: G11C16/04
CPC classification number: G11C16/10
Abstract: A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device.
Abstract translation: 通过将编程电压施加到包括目标存储器单元的字线，确定目标存储器单元是否被编程来编程存储器件的目标存储器单元，并且如果确定所述编程电压被确定为 目标存储单元未编程。 在制造存储器件之后，可以选择初始编程电压和阶跃电压。
-
公开(公告)号：US20120069659A1
公开(公告)日：2012-03-22
申请号：US13308405
申请日：2011-11-30
Applicant: Jin-Man Han , Aaron Yip
Inventor： Jin-Man Han , Aaron Yip
CPC classification number: G11C29/846 , G11C29/82 , G11C2216/30
Abstract: Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of columns. Each of the columns includes a bit line and a plurality of memory cells on the bit line. The plurality of columns include a plurality of groups of regular columns and a plurality of groups of redundant columns. The apparatus also includes a plurality of data latches. Each of the data latches is configured to store data read from a respective one group of regular columns. The apparatus further includes a plurality of redundant data latches. Each of the redundant data latches is configured to store data read from a respective one group of redundant columns. The apparatus also includes a multiplexer configured to selectively output data from the plurality of data latches and the plurality of redundant data latches.
Abstract translation: 公开了装置和方法，例如涉及闪存装置的装置和方法。 一种这样的装置包括包括多个列的存储块。 每个列包括位线和位线上的多个存储单元。 多个列包括多组常规列和多组冗余列。 该装置还包括多个数据锁存器。 每个数据锁存器被配置为存储从相应的一组常规列读取的数据。 该装置还包括多个冗余数据锁存器。 每个冗余数据锁存器被配置为存储从相应的一组冗余列读取的数据。 该装置还包括多路复用器，其被配置为选择性地从多个数据锁存器和多个冗余数据锁存器输出数据。
-
15.发明授权公开(公告)号：US08064258B2
公开(公告)日：2011-11-22
申请号：US12468723
申请日：2009-05-19
Applicant: Jin-Man Han
Inventor： Jin-Man Han
IPC: G11C16/06
CPC classification number: G11C8/20 , G06F11/1068 , G11C8/10 , G11C29/808 , G11C2029/0411
Abstract: A method, apparatus and system providing a memory device having an array of cells which may be selectively designated for either error correction code use or redundancy cell use.
Abstract translation: 一种提供存储器件的方法，装置和系统，该存储器件具有可选择性地指定用于纠错码使用或冗余单元使用的单元阵列。
-
Patent Agency Ranking
公开(公告)号：US20090244982A1
公开(公告)日：2009-10-01
申请号：US12478877
申请日：2009-06-05
Applicant: Jin-Man Han , Aaron Yip
Inventor： Jin-Man Han , Aaron Yip
CPC classification number: G11C8/08 , G06F12/0246 , G11C16/0483 , G11C16/08 , G11C16/3418 , G11C16/3427 , G11C29/76 , G11C29/82 , Y02D10/13
Abstract: A non-volatile memory device has the pages of a certain memory block reallocated to other blocks in order to increase decrease disturb and increase reliability. Each of the reallocation blocks that contain the reallocated pages from the desired memory block are coupled to a wordline driver. These wordline drivers have a subset of the global wordlines as inputs. The desired wordline driver is selected by an appropriate select signal from a block decoder and an indication on an appropriate global wordline. This causes the wordline driver to generate a local wordline to the desired block with the reallocated page to be accessed.
Abstract translation: 非易失性存储器件具有将特定存储器块的页面重新分配给其他块，以便增加减少的干扰并增加可靠性。 包含来自期望的存储器块的重新分配的页面的每个重新分配块被耦合到字线驱动器。 这些字线驱动器具有全局字线的一部分作为输入。 期望的字线驱动器通过来自块解码器的适当选择信号和适当的全局字线上的指示来选择。 这将导致字线驱动程序在要重新分配的页面访问期望块时生成本地字线。
-
公开(公告)号：US20090154247A1
公开(公告)日：2009-06-18
申请号：US12370810
申请日：2009-02-13
Applicant: Dzung H. Nguyen , Benjamin Louie , Hagop A. Nazarian , Aaron Yip , Jin-Man Han
Inventor： Dzung H. Nguyen , Benjamin Louie , Hagop A. Nazarian , Aaron Yip , Jin-Man Han
CPC classification number: G11C16/10
Abstract: A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device.
Abstract translation: 通过将编程电压施加到包括目标存储器单元的字线，确定目标存储器单元是否被编程来编程存储器件的目标存储器单元，并且如果确定所述编程电压被确定为 目标存储单元未编程。 在制造存储器件之后，可以选择初始编程电压和阶跃电压。
-
公开(公告)号：US07542336B2
公开(公告)日：2009-06-02
申请号：US12107315
申请日：2008-04-22
Applicant: Jin-Man Han
Inventor： Jin-Man Han
IPC: G11C16/04
CPC classification number: G11C7/18 , G11C7/02 , G11C16/0483 , G11C16/3418 , G11C16/3427
Abstract: A NAND memory architecture arranges all even bitlines of a page together, and arranges all odd bitlines of a page together, so that programming operations are carried out on adjacent bitlines on the same word line to reduce floating gate coupling. Non-connected bitlines can be used at boundaries between even and odd sections of the array to further reduce floating gate coupling.
Abstract translation: NAND存储器架构将页面的所有偶数位线布置在一起，并且将页面的所有奇数位线布置在一起，使得在相同字线上的相邻位线上执行编程操作以减少浮动栅极耦合。 可以在阵列的偶数和奇数部分之间的边界处使用非连接的位线，以进一步减少浮动栅极耦合。
-
公开(公告)号：US07518914B2
公开(公告)日：2009-04-14
申请号：US11500153
申请日：2006-08-07
Applicant: Jin-Man Han
Inventor： Jin-Man Han
IPC: G11C11/34
CPC classification number: G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C2211/5641
Abstract: A non-volatile memory array with both single level cells and multilevel cells. The single level and multilevel cells, in one embodiment, are alternated either along each bit line. An alternate embodiment alternates the single and multilevel cells along both the bit lines and the word lines so that no single level cell is adjacent to another single level cell in either the word line or the bit line directions.
Abstract translation: 具有单级单元和多级单元的非易失性存储器阵列。 在一个实施例中，单电平和多电平电池沿着每个位线交替。 一个替代实施例沿着位线和字线交替单电层和多电平单元，使得没有单层单元与字线或位线方向上的另一单级单元相邻。
-
公开(公告)号：US07372715B2
公开(公告)日：2008-05-13
申请号：US11452697
申请日：2006-06-14
Applicant: Jin-Man Han
Inventor： Jin-Man Han
IPC: G11C5/06
CPC classification number: G11C7/18 , G11C7/02 , G11C16/0483 , G11C16/3418 , G11C16/3427
Abstract: A NAND memory architecture arranges all even bitlines of a page together, and arranges all odd bitlines of a page together, so that programming operations are carried out on adjacent bitlines on the same word line to reduce floating gate coupling. Non-connected bitlines can be used at boundaries between even and odd sections of the array to further reduce floating gate coupling.
Abstract translation: NAND存储器架构将页面的所有偶数位线布置在一起，并且将页面的所有奇数位线布置在一起，使得在相同字线上的相邻位线上执行编程操作以减少浮动栅极耦合。 可以在阵列的偶数和奇数部分之间的边界处使用非连接的位线，以进一步减少浮动栅极耦合。
-
-
-
-
-
-
-
-
-
Search Results
79
records
(took 0.022 seconds)
