公开(公告)号：US20150294980A1

公开(公告)日：2015-10-15

申请号：US14681505

申请日：2015-04-08

申请人： Jaegoo Lee ,  Youngwoo Park ,  Jaeduk Lee

发明人： Jaegoo Lee ,  Youngwoo Park ,  Jaeduk Lee

IPC分类号： H01L27/115 ,  H01L29/66 ,  H01L21/285 ,  H01L21/28 ,  H01L21/768 ,  H01L29/792 ,  H01L29/423

CPC分类号： H01L27/11582 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/76877 ,  H01L29/66833 ,  H01L29/7926

摘要： Semiconductor devices are provided including an active pillar protruding from a substrate; a first gate electrode and a second gate electrode adjacent to a sidewall of the active pillar and vertically overlapping with each other, the first and second gate electrodes being insulated from each other; a first intergate insulating layer covering a first surface of the first gate electrode; and a second intergate insulating layer covering a second surface, opposite the first surface, of the second gate electrode and spaced apart from the first intergate insulating layer. The first intergate insulating layer and the second intergate insulating layer define an air gap therebetween.

摘要翻译： 提供半导体器件，其包括从基板突出的有源柱; 与所述有源柱的侧壁相邻并且彼此垂直重叠的第一栅电极和第二栅电极，所述第一栅电极和所述第二栅电极彼此绝缘; 覆盖所述第一栅电极的第一表面的第一隔间绝缘层; 以及覆盖所述第二栅电极的与所述第一表面相对的第二表面并与所述第一栅极绝缘层间隔开的第二栅极绝缘层。 第一隔间绝缘层和第二隔间绝缘层在其间形成气隙。

公开(公告)号：US10418278B2

公开(公告)日：2019-09-17

申请号：US15857961

申请日：2017-12-29

申请人： Dohyun Lee ,  Youngwoo Park ,  Junghoon Park ,  Jaeduk Lee

发明人： Dohyun Lee ,  Youngwoo Park ,  Junghoon Park ,  Jaeduk Lee

IPC分类号： H01L21/00 ,  H01L21/768 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/532 ,  H01L27/11573 ,  H01L27/11575 ,  H01L23/528

摘要： A semiconductor device includes a semiconductor pattern on a semiconductor substrate, a three-dimensional memory array on the semiconductor pattern, and a peripheral interconnection structure between the semiconductor pattern and the semiconductor substrate. The peripheral interconnection structure includes an upper interconnection structure on a lower interconnection structure. The upper interconnection structure includes an upper interconnection and an upper barrier layer. The lower interconnection structure includes a lower interconnection and a lower barrier layer. The upper barrier layer is under a bottom surface of the upper interconnection and does not cover side surfaces of the upper interconnection. The lower barrier layer is under a bottom surface of the lower interconnection and covers side surfaces of the lower interconnection.

公开(公告)号：US10056404B2

公开(公告)日：2018-08-21

申请号：US14989955

申请日：2016-01-07

申请人： Jaeduk Lee ,  Youngwoo Park

发明人： Jaeduk Lee ,  Youngwoo Park

IPC分类号： H01L29/792 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/06

CPC分类号： H01L27/11582 ,  H01L27/0688 ,  H01L27/11573

摘要： The inventive concepts relate to a semiconductor memory device. The semiconductor memory device includes a substrate including a circuit region and first and second connection regions respectively disposed at both sides of the circuit region opposite to each other, a logic structure including a logic circuit disposed on the circuit region and a lower insulating layer covering the logic circuit, and a memory structure on the logic structure. The logic circuit includes a first page buffer disposed adjacently to the first connection region and a second page buffer disposed adjacently to the second connection region. The memory structure includes bit lines extending onto at least one of the first and second connection regions.

公开(公告)号：US20170011996A1

公开(公告)日：2017-01-12

申请号：US15201922

申请日：2016-07-05

申请人： Dohyun LEE ,  Youngwoo Park ,  Junghoon Park ,  Jaeduk Lee

发明人： Dohyun LEE ,  Youngwoo Park ,  Junghoon Park ,  Jaeduk Lee

IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L27/115

CPC分类号： H01L21/76877 ,  H01L21/76816 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53266 ,  H01L23/53295 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

摘要： A semiconductor device includes a semiconductor pattern on a semiconductor substrate, a three-dimensional memory array on the semiconductor pattern, and a peripheral interconnection structure between the semiconductor pattern and the semiconductor substrate. The peripheral interconnection structure includes an upper interconnection structure on a lower interconnection structure. The upper interconnection structure includes an upper interconnection and an upper barrier layer. The lower interconnection structure includes a lower interconnection and a lower barrier layer. The upper barrier layer is under a bottom surface of the upper interconnection and does not cover side surfaces of the upper interconnection. The lower barrier layer is under a bottom surface of the lower interconnection and covers side surfaces of the lower interconnection.

摘要翻译： 半导体器件包括在半导体衬底上的半导体图案，半导体图案上的三维存储器阵列以及半导体图案和半导体衬底之间的外围互连结构。 外围互连结构包括在较低互连结构上的上互连结构。 上互连结构包括上互连和上阻挡层。 下部互连结构包括下部互连和下部阻挡层。 上阻挡层在上互连的底表面下方并且不覆盖上互连的侧表面。 下阻挡层在下互连的底表面下方并且覆盖下互连的侧表面。

公开(公告)号：US20160005760A1

公开(公告)日：2016-01-07

申请号：US14725476

申请日：2015-05-29

申请人： Dohyun Lee ,  Jaegoo Lee ,  Young-Jin Kwon ,  Youngwoo Park ,  Jaeduk Lee

发明人： Dohyun Lee ,  Jaegoo Lee ,  Young-Jin Kwon ,  Youngwoo Park ,  Jaeduk Lee

IPC分类号： H01L27/115 ,  H01L29/10 ,  H01L29/792

CPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L29/1033 ,  H01L29/7926

摘要： A semiconductor device includes a lower stack structure including lower gate electrodes and lower insulating layers that are alternately and repeatedly stacked on a substrate. The semiconductor device includes an upper stack structure including upper gate electrodes and upper insulating layers that are alternately and repeatedly stacked on the lower stack structure. A lower channel structure penetrates the lower stack structure. An upper channel structure penetrates and is connected to the upper stack structure. A lower vertical insulator is disposed between the lower stack structure and the lower channel structure. The lower channel structure includes a first vertical semiconductor pattern connected to the substrate, and a first connecting semiconductor pattern disposed on the first vertical semiconductor pattern. The upper channel structure includes a second vertical semiconductor pattern electrically connected to the first vertical semiconductor pattern with the first connecting semiconductor pattern disposed therebetween.

摘要翻译： 半导体器件包括下层堆叠结构，其包括交替重复堆叠在衬底上的下栅电极和下绝缘层。 半导体器件包括上堆叠结构，其包括交替重复堆叠在下堆叠结构上的上栅电极和上绝缘层。 下部通道结构穿透下部堆叠结构。 上通道结构穿透并连接到上堆叠结构。 下部垂直绝缘体设置在下部堆叠结构和下部通道结构之间。 下通道结构包括连接到基板的第一垂直半导体图案和布置在第一垂直半导体图案上的第一连接半导体图案。 上通道结构包括电连接到第一垂直半导体图案的第二垂直半导体图案，其间设置有第一连接半导体图案。

公开(公告)号：US08368138B2

公开(公告)日：2013-02-05

申请号：US12884668

申请日：2010-09-17

申请人： Yong-Lack Choi ,  Sunghoi Hur ,  Jaeduk Lee ,  Jungdal Choi

发明人： Yong-Lack Choi ,  Sunghoi Hur ,  Jaeduk Lee ,  Jungdal Choi

IPC分类号： H01L29/788

CPC分类号： H01L29/7883 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42336

摘要： Semiconductor devices and methods of forming the same. The semiconductor devices include a tunnel insulation layer on a substrate, a floating gate on the tunnel insulation layer, a gate insulation layer on the floating gate, a low-dielectric constant (low-k) region between the top of the floating gate and the gate insulation layer, the low-k region having a lower dielectric constant than a silicon oxide, and a control gate on the gate insulation layer.

摘要翻译： 半导体器件及其形成方法。 半导体器件包括在衬底上的隧道绝缘层，隧道绝缘层上的浮动栅极，浮置栅极上的栅极绝缘层，浮动栅极的顶部和第二栅极之间的低介电常数（低k）区域 栅极绝缘层，具有比氧化硅更低的介电常数的低k区域以及栅极绝缘层上的控制栅极。

公开(公告)号：US20110079839A1

公开(公告)日：2011-04-07

申请号：US12894863

申请日：2010-09-30

申请人： Fayrushin Albert ,  Kwang Soo Seol ,  Jaeduk Lee

发明人： Fayrushin Albert ,  Kwang Soo Seol ,  Jaeduk Lee

IPC分类号： H01L29/788

CPC分类号： H01L29/4234 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/792

摘要： Provided is a semiconductor device. The semiconductor device includes a substrate, a tunnel insulating layer, a charge storage pattern, a blocking layer, a gate electrode. The tunnel insulating layer is disposed over the substrate. The charge storage pattern is disposed over the tunnel insulating layer. The charge storage pattern has an upper surface, a sidewall, and an edge portion between the upper surface and the sidewall. The blocking layer includes an insulating pattern covering the edge portion of the charge storage pattern, and a gate dielectric layer covering the upper surface, the sidewall, and the edge portion of the charge storage pattern. The gate electrode is disposed over the blocking layer, the gate electrode covering the upper surface, the sidewall, and the edge portion of the charge storage pattern.

摘要翻译： 提供一种半导体器件。 半导体器件包括衬底，隧道绝缘层，电荷存储图案，阻挡层，栅电极。 隧道绝缘层设置在衬底上。 电荷存储图案设置在隧道绝缘层上。 电荷存储图案具有在上表面和侧壁之间的上表面，侧壁和边缘部分。 阻挡层包括覆盖电荷存储图案的边缘部分的绝缘图案，以及覆盖电荷存储图案的上表面，侧壁和边缘部分的栅极电介质层。 栅电极设置在阻挡层上，栅电极覆盖电荷存储图案的上表面，侧壁和边缘部分。

公开(公告)号：US08791520B2

公开(公告)日：2014-07-29

申请号：US12986553

申请日：2011-01-07

申请人： Jaeduk Lee ,  Albert Fayrushin ,  ByungKyu Cho ,  Jungdal Choi ,  Sunghoi Hur ,  Kwang Soo Seol ,  Dohyun Lee

发明人： Jaeduk Lee ,  Albert Fayrushin ,  ByungKyu Cho ,  Jungdal Choi ,  Sunghoi Hur ,  Kwang Soo Seol ,  Dohyun Lee

IPC分类号： H01L29/788 ,  H01L29/792

CPC分类号： H01L29/42336 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42352 ,  H01L29/7881 ,  H01L29/792

摘要： Provided are nonvolatile memory devices and a method of forming the same. A tunnel insulating pattern is provided on a substrate, and a floating gate is provided on the tunnel insulating pattern. A floating gate cap having a charge trap site is provided on the floating gate, and a gate dielectric pattern is provided on the floating gate cap. A control gate is provided on the gate dielectric pattern.

摘要翻译： 提供了非易失性存储器件及其形成方法。 隧道绝缘图案设置在基板上，并且浮动栅极设置在隧道绝缘图案上。 在浮置栅极上设置具有电荷陷阱位置的浮动栅极盖，并且在浮动栅极盖上设置栅极电介质图案。 控制栅极设置在栅极电介质图案上。

公开(公告)号：US20110073928A1

公开(公告)日：2011-03-31

申请号：US12894844

申请日：2010-09-30

申请人： ByungKyu Cho ,  Sunghoi Hur ,  Jaeduk Lee ,  Jungdal Choi

发明人： ByungKyu Cho ,  Sunghoi Hur ,  Jaeduk Lee ,  Jungdal Choi

IPC分类号： H01L29/788

CPC分类号： H01L29/42324 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/7881

摘要： Provided are a non-volatile memory device and a method of forming the same. The non-volatile memory device includes: a tunnel insulation layer on a substrate; a floating gate on the tunnel insulation layer; a blocking insulation layer on the floating gate; a first barrier pattern, between the top of the floating gate and the blocking insulation layer, having a higher conduction band energy level than the floating gate; and a control gate on the blocking insulation layer.

摘要翻译： 提供一种非易失性存储器件及其形成方法。 非易失性存储器件包括：衬底上的隧道绝缘层; 隧道绝缘层上的浮栅; 浮栅上的阻挡绝缘层; 在浮置栅极的顶部和阻挡绝缘层之间的第一阻挡图案具有比浮动栅极更高的导带能级; 和阻挡绝缘层上的控制栅极。