公开(公告)号：US20160005760A1

公开(公告)日：2016-01-07

申请号：US14725476

申请日：2015-05-29

申请人： Dohyun Lee ,  Jaegoo Lee ,  Young-Jin Kwon ,  Youngwoo Park ,  Jaeduk Lee

发明人： Dohyun Lee ,  Jaegoo Lee ,  Young-Jin Kwon ,  Youngwoo Park ,  Jaeduk Lee

IPC分类号： H01L27/115 ,  H01L29/10 ,  H01L29/792

CPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L29/1033 ,  H01L29/7926

摘要： A semiconductor device includes a lower stack structure including lower gate electrodes and lower insulating layers that are alternately and repeatedly stacked on a substrate. The semiconductor device includes an upper stack structure including upper gate electrodes and upper insulating layers that are alternately and repeatedly stacked on the lower stack structure. A lower channel structure penetrates the lower stack structure. An upper channel structure penetrates and is connected to the upper stack structure. A lower vertical insulator is disposed between the lower stack structure and the lower channel structure. The lower channel structure includes a first vertical semiconductor pattern connected to the substrate, and a first connecting semiconductor pattern disposed on the first vertical semiconductor pattern. The upper channel structure includes a second vertical semiconductor pattern electrically connected to the first vertical semiconductor pattern with the first connecting semiconductor pattern disposed therebetween.

摘要翻译： 半导体器件包括下层堆叠结构，其包括交替重复堆叠在衬底上的下栅电极和下绝缘层。 半导体器件包括上堆叠结构，其包括交替重复堆叠在下堆叠结构上的上栅电极和上绝缘层。 下部通道结构穿透下部堆叠结构。 上通道结构穿透并连接到上堆叠结构。 下部垂直绝缘体设置在下部堆叠结构和下部通道结构之间。 下通道结构包括连接到基板的第一垂直半导体图案和布置在第一垂直半导体图案上的第一连接半导体图案。 上通道结构包括电连接到第一垂直半导体图案的第二垂直半导体图案，其间设置有第一连接半导体图案。

公开(公告)号：US09362303B2

公开(公告)日：2016-06-07

申请号：US14681505

申请日：2015-04-08

申请人： Jaegoo Lee ,  Youngwoo Park ,  Jaeduk Lee

发明人： Jaegoo Lee ,  Youngwoo Park ,  Jaeduk Lee

IPC分类号： H01L29/792 ,  H01L27/115 ,  H01L29/66 ,  H01L21/28 ,  H01L21/768 ,  H01L21/285

CPC分类号： H01L27/11582 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/76877 ,  H01L29/66833 ,  H01L29/7926

摘要： Semiconductor devices are provided including an active pillar protruding from a substrate; a first gate electrode and a second gate electrode adjacent to a sidewall of the active pillar and vertically overlapping with each other, the first and second gate electrodes being insulated from each other; a first intergate insulating layer covering a first surface of the first gate electrode; and a second intergate insulating layer covering a second surface, opposite the first surface, of the second gate electrode and spaced apart from the first intergate insulating layer. The first intergate insulating layer and the second intergate insulating layer define an air gap therebetween.

摘要翻译： 提供半导体器件，其包括从基板突出的有源柱; 与所述有源柱的侧壁相邻并且彼此垂直重叠的第一栅电极和第二栅电极，所述第一栅电极和所述第二栅电极彼此绝缘; 覆盖所述第一栅电极的第一表面的第一隔间绝缘层; 以及覆盖所述第二栅电极的与所述第一表面相对的第二表面并与所述第一栅极绝缘层间隔开的第二栅极绝缘层。 第一隔间绝缘层和第二隔间绝缘层在其间形成气隙。

公开(公告)号：US20150294980A1

公开(公告)日：2015-10-15

申请号：US14681505

申请日：2015-04-08

申请人： Jaegoo Lee ,  Youngwoo Park ,  Jaeduk Lee

发明人： Jaegoo Lee ,  Youngwoo Park ,  Jaeduk Lee

IPC分类号： H01L27/115 ,  H01L29/66 ,  H01L21/285 ,  H01L21/28 ,  H01L21/768 ,  H01L29/792 ,  H01L29/423

CPC分类号： H01L27/11582 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/76877 ,  H01L29/66833 ,  H01L29/7926

摘要： Semiconductor devices are provided including an active pillar protruding from a substrate; a first gate electrode and a second gate electrode adjacent to a sidewall of the active pillar and vertically overlapping with each other, the first and second gate electrodes being insulated from each other; a first intergate insulating layer covering a first surface of the first gate electrode; and a second intergate insulating layer covering a second surface, opposite the first surface, of the second gate electrode and spaced apart from the first intergate insulating layer. The first intergate insulating layer and the second intergate insulating layer define an air gap therebetween.

摘要翻译： 提供半导体器件，其包括从基板突出的有源柱; 与所述有源柱的侧壁相邻并且彼此垂直重叠的第一栅电极和第二栅电极，所述第一栅电极和所述第二栅电极彼此绝缘; 覆盖所述第一栅电极的第一表面的第一隔间绝缘层; 以及覆盖所述第二栅电极的与所述第一表面相对的第二表面并与所述第一栅极绝缘层间隔开的第二栅极绝缘层。 第一隔间绝缘层和第二隔间绝缘层在其间形成气隙。

公开(公告)号：US09875931B2

公开(公告)日：2018-01-23

申请号：US15201922

申请日：2016-07-05

申请人： Dohyun Lee ,  Youngwoo Park ,  Junghoon Park ,  Jaeduk Lee

发明人： Dohyun Lee ,  Youngwoo Park ,  Junghoon Park ,  Jaeduk Lee

IPC分类号： H01L21/00 ,  H01L21/768 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/76877 ,  H01L21/76816 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53266 ,  H01L23/53295 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

摘要： A semiconductor device includes a semiconductor pattern on a semiconductor substrate, a three-dimensional memory array on the semiconductor pattern, and a peripheral interconnection structure between the semiconductor pattern and the semiconductor substrate. The peripheral interconnection structure includes an upper interconnection structure on a lower interconnection structure. The upper interconnection structure includes an upper interconnection and an upper barrier layer. The lower interconnection structure includes a lower interconnection and a lower barrier layer. The upper barrier layer is under a bottom surface of the upper interconnection and does not cover side surfaces of the upper interconnection. The lower barrier layer is under a bottom surface of the lower interconnection and covers side surfaces of the lower interconnection.

公开(公告)号：US09299707B2

公开(公告)日：2016-03-29

申请号：US14150452

申请日：2014-01-08

申请人： Jaeduk Lee ,  Youngwoo Park ,  Jintaek Park ,  Dohyun Lee ,  Kohji Kanamori

发明人： Jaeduk Lee ,  Youngwoo Park ,  Jintaek Park ,  Dohyun Lee ,  Kohji Kanamori

IPC分类号： H01L27/108 ,  H01L27/105 ,  H01L27/115 ,  G11C16/10 ,  G11C16/14

CPC分类号： H01L27/1052 ,  G11C16/10 ,  G11C16/14 ,  H01L27/11524 ,  H01L27/11556

摘要： Provided are three-dimensional semiconductor devices and methods of operating the same. The three-dimensional semiconductor devices may include active patterns arranged on a substrate to have a multi-layered and multi-column structure and drain patterns connected to respective columns of the active patterns. The methods may include a layer-selection step connecting a selected one of layers of the active patterns selectively to the drain patterns. For example, the layer-selection step may be performed in such a way that widths of depletion regions to be formed in end-portions of the active patterns are differently controlled depending on to a height from the substrate.

摘要翻译： 提供三维半导体器件及其操作方法。 三维半导体器件可以包括布置在衬底上的有源图案，以具有连接到有源图案的相应列的多层和多列结构以及漏极图案。 所述方法可以包括选择性地将有源图案的层中所选择的一个层连接到漏极图案的层选择步骤。 例如，层选择步骤可以以这样的方式执行，使得在有源图案的端部中形成的耗尽区的宽度根据与基板的高度不同地被控制。

公开(公告)号：US10418278B2

公开(公告)日：2019-09-17

申请号：US15857961

申请日：2017-12-29

申请人： Dohyun Lee ,  Youngwoo Park ,  Junghoon Park ,  Jaeduk Lee

发明人： Dohyun Lee ,  Youngwoo Park ,  Junghoon Park ,  Jaeduk Lee

IPC分类号： H01L21/00 ,  H01L21/768 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/532 ,  H01L27/11573 ,  H01L27/11575 ,  H01L23/528

摘要： A semiconductor device includes a semiconductor pattern on a semiconductor substrate, a three-dimensional memory array on the semiconductor pattern, and a peripheral interconnection structure between the semiconductor pattern and the semiconductor substrate. The peripheral interconnection structure includes an upper interconnection structure on a lower interconnection structure. The upper interconnection structure includes an upper interconnection and an upper barrier layer. The lower interconnection structure includes a lower interconnection and a lower barrier layer. The upper barrier layer is under a bottom surface of the upper interconnection and does not cover side surfaces of the upper interconnection. The lower barrier layer is under a bottom surface of the lower interconnection and covers side surfaces of the lower interconnection.

公开(公告)号：US20170011996A1

公开(公告)日：2017-01-12

申请号：US15201922

申请日：2016-07-05

申请人： Dohyun LEE ,  Youngwoo Park ,  Junghoon Park ,  Jaeduk Lee

发明人： Dohyun LEE ,  Youngwoo Park ,  Junghoon Park ,  Jaeduk Lee

IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L27/115

CPC分类号： H01L21/76877 ,  H01L21/76816 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53266 ,  H01L23/53295 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

摘要： A semiconductor device includes a semiconductor pattern on a semiconductor substrate, a three-dimensional memory array on the semiconductor pattern, and a peripheral interconnection structure between the semiconductor pattern and the semiconductor substrate. The peripheral interconnection structure includes an upper interconnection structure on a lower interconnection structure. The upper interconnection structure includes an upper interconnection and an upper barrier layer. The lower interconnection structure includes a lower interconnection and a lower barrier layer. The upper barrier layer is under a bottom surface of the upper interconnection and does not cover side surfaces of the upper interconnection. The lower barrier layer is under a bottom surface of the lower interconnection and covers side surfaces of the lower interconnection.

摘要翻译： 半导体器件包括在半导体衬底上的半导体图案，半导体图案上的三维存储器阵列以及半导体图案和半导体衬底之间的外围互连结构。 外围互连结构包括在较低互连结构上的上互连结构。 上互连结构包括上互连和上阻挡层。 下部互连结构包括下部互连和下部阻挡层。 上阻挡层在上互连的底表面下方并且不覆盖上互连的侧表面。 下阻挡层在下互连的底表面下方并且覆盖下互连的侧表面。

公开(公告)号：US20140197469A1

公开(公告)日：2014-07-17

申请号：US14150452

申请日：2014-01-08

申请人： Jaeduk Lee ,  Youngwoo Park ,  Jintaek Park ,  Dohyun Lee ,  Kohji Kanamori

发明人： Jaeduk Lee ,  Youngwoo Park ,  Jintaek Park ,  Dohyun Lee ,  Kohji Kanamori

IPC分类号： H01L27/105

CPC分类号： H01L27/1052 ,  G11C16/10 ,  G11C16/14 ,  H01L27/11524 ,  H01L27/11556

摘要： Provided are three-dimensional semiconductor devices and methods of operating the same. The three-dimensional semiconductor devices may include active patterns arranged on a substrate to have a multi-layered and multi-column structure and drain patterns connected to respective columns of the active patterns. The methods may include a layer-selection step connecting a selected one of layers of the active patterns selectively to the drain patterns. For example, the layer-selection step may be performed in such a way that widths of depletion regions to be formed in end-portions of the active patterns are differently controlled depending on to a height from the substrate.

摘要翻译： 提供三维半导体器件及其操作方法。 三维半导体器件可以包括布置在衬底上的有源图案，以具有连接到有源图案的相应列的多层和多列结构以及漏极图案。 所述方法可以包括选择性地将有源图案的层中所选择的一个层连接到漏极图案的层选择步骤。 例如，层选择步骤可以以这样的方式执行，使得在有源图案的端部中形成的耗尽区的宽度根据与基板的高度不同地被控制。

公开(公告)号：US20120119283A1

公开(公告)日：2012-05-17

申请号：US13238319

申请日：2011-09-21

申请人： Jaegoo Lee ,  Youngwoo Park

发明人： Jaegoo Lee ,  Youngwoo Park

IPC分类号： H01L29/78 ,  H01L29/792 ,  H01L29/788

CPC分类号： H01L21/76832 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582

摘要： A plurality of vertical channels of semiconductor material are formed to extend in a vertical direction through the plurality of insulation layers and the plurality of conductive patterns, a gate insulating layer between the conductive pattern and the vertical channels that insulates the conductive pattern from the vertical channels. Conductive contact regions of the at least two of the conductive patterns are in a stepped configuration. An etch stop layer is positioned on the conductive contact regions, wherein the etch stop layer has a first portion on a first one of the plurality of conductive patterns and has a second portion on a second one of the plurality of conductive patterns, wherein the first portion is of a thickness that is greater than a thickness of the second portion.

摘要翻译： 多个垂直通道的半导体材料形成为沿着垂直方向延伸穿过多个绝缘层和多个导电图案，导电图案和垂直沟道之间的栅极绝缘层将导电图案与垂直沟道绝缘 。 至少两个导电图案的导电接触区域处于阶梯状结构。 蚀刻停止层位于导电接触区域上，其中蚀刻停止层在多个导电图案中的第一个上具有第一部分，并且在多个导电图案中的第二个导电图案上具有第二部分，其中第一部分 部分的厚度大于第二部分的厚度。

公开(公告)号：US08822322B2

公开(公告)日：2014-09-02

申请号：US13214462

申请日：2011-08-22

申请人： Jaegoo Lee ,  Youngwoo Park ,  Jungdal Choi

发明人： Jaegoo Lee ,  Youngwoo Park ,  Jungdal Choi

IPC分类号： H01L21/8239

CPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/4234 ,  H01L29/7827 ,  H01L29/7926

摘要： A method of fabricating a semiconductor memory device includes forming a mold stack on a substrate and the mold stack including first sacrificial layers and second sacrificial layers alternately stacked on the substrate. The method also includes forming a plurality of vertical channels that penetrate the mold stack and that contact the substrate, patterning the mold stack to form word line cuts between the vertical channels, the word line cuts exposing the substrate, removing one of the first and second sacrificial layers to form recessed regions in the mold stack, forming a data storage layer, at least a portion of the data storage layer being formed between the vertical channels and the gates, forming gates in the recessed regions, forming air gaps between the gates by removing the other of the first and second sacrificial layers, and forming an insulation layer pattern in the word line cuts.

摘要翻译： 一种制造半导体存储器件的方法包括在衬底上形成模具堆叠，并且模具叠层包括交替层叠在衬底上的第一牺牲层和第二牺牲层。 该方法还包括形成多个垂直通道，其穿过模具叠层并与衬底接触，图案化模具叠层以形成垂直通道之间的字线切口，字线切割暴露衬底，去除第一和第二 牺牲层，以在模具堆叠中形成凹陷区域，形成数据存储层，数据存储层的至少一部分形成在垂直沟道和栅极之间，在凹陷区域中形成栅极，在栅极之间形成气隙，通过 去除第一和第二牺牲层中的另一个，并且在字线切割中形成绝缘层图案。