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公开(公告)号：US20230213993A1
公开(公告)日：2023-07-06
申请号：US18181488
申请日：2023-03-09
Applicant: Kioxia Corporation
Inventor： Akio SUGAHARA , Yasuhiro HIRASHIMA , Naoya TOKIWA
IPC: G06F1/28
CPC classification number: G06F1/28 , G11C16/0483
Abstract: According to an embodiment, a semiconductor memory device includes a first pin, a first receiving circuit, and a first terminating circuit. The first pin receives a first signal and a second signal having a smaller amplitude than the first signal. The first receiving circuit is connected to the first pin and outputs, based on a comparison between the first signal and a first voltage, a third signal. The first receiving circuit also outputs, based on a comparison between the second signal and a second voltage, a fourth signal having a smaller amplitude than the third signal. The first terminating circuit is connected to the first pin. The first terminating circuit is disabled if the first pin receives the first signal, and enabled if the first pin receives the second signal.
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公开(公告)号：US20230052383A1
公开(公告)日：2023-02-16
申请号：US17973549
申请日：2022-10-26
Applicant: Kioxia Corporation
Inventor： Akio SUGAHARA , Akihiro IMAMOTO , Toshifumi WATANABE , Mami KAKOI , Kohei MASUDA , Masahiro YOSHIHARA , Naofumi ABIKO
Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.
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公开(公告)号：US20210335398A1
公开(公告)日：2021-10-28
申请号：US17164273
申请日：2021-02-01
Applicant: Kioxia Corporation
Inventor： Akio SUGAHARA
IPC: G11C7/10
Abstract: According to one embodiment, a semiconductor memory device includes: a first plane PL0 including a first memory cell array 57A, and a first latch circuit 60A configured to store first read data read from the first memory cell array 57A; a second plane PL1 including a second memory cell array 57B, and a second latch circuit 60B configured to store second read data read from the second memory cell array 57B; and an I/O circuit 11 including a first FIFO circuit 14A configured to fetch the first read data from the first latch circuit 60A, and a second FIFO circuit 14B configured to fetch the second read data from the second latch circuit 60B.
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公开(公告)号：US20210202007A1
公开(公告)日：2021-07-01
申请号：US17200996
申请日：2021-03-15
Applicant: Kioxia Corporation
Inventor： Akio SUGAHARA , Akihiro IMAMOTO , Toshifumi WATANABE , Mami KAKOI , Kohei MASUDA , Masahiro YOSHIHARA , Naofumi ABIKO
Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation, and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.
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公开(公告)号：US20210090643A1
公开(公告)日：2021-03-25
申请号：US17018684
申请日：2020-09-11
Applicant: Kioxia Corporation
Inventor： Naomi TAKEDA , Masanobu SHIRAKAWA , Akio SUGAHARA
Abstract: According to one embodiment, a memory system includes n memory cells, each capable of storing j bits of data; and a controller. The controller is configured to write a first portion of each of first data to n-th data from among n×j data with consecutive logical addresses to the n memory cells one by one. The first data has a lowest logical address among the n×j pieces of data. The first data to the n-th data have ascending consecutive logical addresses. The controller is configured to write the first portion of one of the first to n-th data as a first bit of the j bits, and write the first portion of another one of the first to n-th data except said one of the first to n-th data as a second bit of the j bits.
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Patent Agency Ranking
16.发明申请公开(公告)号：US20250046384A1
公开(公告)日：2025-02-06
申请号：US18923698
申请日：2024-10-23
Applicant: Kioxia Corporation
Inventor： Akio SUGAHARA , Takaya HANDA , Ryosuke ISOMURA , Kazuto UEHARA , Junichi SATO , Norichika ASAOKA , Masashi YAMAOKA , Bushnaq SANAD , Yuzuru SHIBAZAKI , Noriyasu KUMAZAKI , Yuri TERADA
Abstract: A memory device includes a memory cell array, a voltage generation circuit generating one or more voltages supplied to the memory cell array, an input/output circuit receiving a first command and an address indicating a region in the memory cell array, and a control circuit controlling a read operation to the memory cell array based on the first command. The control circuit supplies a non-selection voltage of the voltages before a ready/busy signal changes from a ready state to a busy state.
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公开(公告)号：US20250036310A1
公开(公告)日：2025-01-30
申请号：US18779832
申请日：2024-07-22
Applicant: Kioxia Corporation
Inventor： Yoshikazu HARADA , Akio SUGAHARA
IPC: G06F3/06 , G06F12/0802
Abstract: A semiconductor storage device includes a memory string, a sense amplifier including first and second latch circuits, a cache memory including a third latch circuit, and a control circuit. The control circuit is configured to perform a first read operation in response to a first command set and consecutively perform a second read operation in response to a second command set received during the first read operation. During the first read operation, data read from the memory string is stored in the first latch circuit. When the second command set is received at a first timing, the control circuit transfers the data to the second latch circuit, and then to the third latch circuit. When the second command set is received at a second timing before the first timing, the control circuit directly transfers the data to the third latch circuit.
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公开(公告)号：US20240221799A1
公开(公告)日：2024-07-04
申请号：US18609522
申请日：2024-03-19
Applicant: KIOXIA CORPORATION
Inventor： Akio SUGAHARA , Yoshikazu HARADA , Shoichiro HASHIMOTO
CPC classification number: G11C7/1063 , G11C5/025 , G11C7/222
Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.
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公开(公告)号：US20240094959A1
公开(公告)日：2024-03-21
申请号：US18524477
申请日：2023-11-30
Applicant: KIOXIA CORPORATION
Inventor： Akio SUGAHARA , Zhao LU , Takehisa KUROSAWA , Yuji NAGAI
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0679 , G11C16/0483 , G11C16/26
Abstract: A semiconductor memory device comprises: a first pad receiving a first signal; a second pad receiving a second signal; a first memory cell array; a first sense amplifier connected to the first memory cell array; a first data register connected to the first sense amplifier and configured to store user data read from the first memory cell array; and a control circuit configured to execute an operation targeting the first memory cell array. The first memory cell array comprises a plurality of first memory strings. The first memory strings each comprise a plurality of first memory cell transistors. In a first mode of this semiconductor memory device, a command set instructing the operation is inputted via the first pad. In a second mode of this semiconductor memory device, the command set is inputted via the second pad.
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公开(公告)号：US20230395144A1
公开(公告)日：2023-12-07
申请号：US18451182
申请日：2023-08-17
Applicant: KIOXIA CORPORATION
Inventor： Naomi TAKEDA , Masanobu SHIRAKAWA , Akio SUGAHARA
CPC classification number: G11C11/5628 , G11C11/5671 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/08 , G06F12/0246
Abstract: According to one embodiment, a memory system includes n memory cells, each capable of storing j bits of data; and a controller. The controller is configured to write a first portion of each of first data to n-th data from among n×j data with consecutive logical addresses to the n memory cells one by one. The first data has a lowest logical address among the n×j pieces of data. The first data to the n-th data have ascending consecutive logical addresses. The controller is configured to write the first portion of one of the first to n-th data as a first bit of the j bits, and write the first portion of another one of the first to n-th data except said one of the first to n-th data as a second bit of the j bits.
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