公开(公告)号：US20230307052A1

公开(公告)日：2023-09-28

申请号：US17901239

申请日：2022-09-01

Applicant: Kioxia Corporation

Inventor： Jun DEGUCHI ,  Daisuke MIYASHITA ,  Atsushi KAWASUMI ,  Hidehiro SHIGA ,  Shinji MIYANO ,  Shinichi SASAKI

IPC: G11C16/08

CPC classification number: G11C16/08

Abstract: A semiconductor storage device includes a memory cell array including a plurality of word line groups and a plurality of blocks corresponding to the plurality of word line groups. Each of word line groups includes a plurality of word lines and each of the blocks includes a plurality of memory cells. The plurality of memory cells of each block are connected to the respective word lines of a corresponding one of the word line groups. The semiconductor storage device includes a row decoder including a plurality of word line group decoders corresponding to the plurality of word line groups, respectively. Each of the plurality of word line group decoders is configured to drive a word line independent from a word line driven in another of the word line groups, when all of the plurality of word line groups are activated in parallel.

公开(公告)号：US20220310159A1

公开(公告)日：2022-09-29

申请号：US17459974

申请日：2021-08-27

Applicant: KIOXIA CORPORATION

Inventor： Hidehiro SHIGA

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C5/06

Abstract: A nonvolatile semiconductor storage device includes first and second semiconductor layers extending in a first direction and spaced apart in a second direction, first and second bit lines extending in the second direction and respectively arranged on opposite sides of the semiconductor layers in the first direction, first and second source lines extending in a third direction and respectively arranged on opposite sides of the semiconductor layers in the first direction, a first memory string including first and second select transistors connected to the first bit line and the first source line, respectively, a second memory string including third and fourth select transistors connected to the second bit line and the second source line, respectively, a first select gate line connected to gates of the first and fourth select transistors, and a second select gate line connected to gates of the second and third select transistors.

公开(公告)号：US20240321352A1

公开(公告)日：2024-09-26

申请号：US18603281

申请日：2024-03-13

Applicant: Kioxia Corporation

Inventor： Ryu OGIWARA ,  Hidehiro SHIGA ,  Daisaburo TAKASHIMA

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C13/0004 ,  G11C13/0064

Abstract: According to one embodiment, a device includes: a memory cell coupled to a bit line and configured to store first data including first, second, and third bits; and a sense amplification circuit configured to perform a first comparison between a bit line voltage and a first reference voltage, and a second comparison between the bit line voltage and a second reference voltage lower than the first reference voltage, and to read the first data from the memory cell based on results of the first and second comparisons. The sense amplification circuit is configured to retain second data having a first code in response to the bit line voltage becoming equal to or lower than the first reference voltage during a first period from a start of operation to a first time point, and retain the first data after the first period.

公开(公告)号：US20240311286A1

公开(公告)日：2024-09-19

申请号：US18601791

申请日：2024-03-11

Applicant: Kioxia Corporation

Inventor： Atsushi KAWASUMI ,  Takashi MAEDA ,  Hidehiro SHIGA

IPC: G06F12/02 ,  G11C16/04 ,  G11C16/26

CPC classification number: G06F12/02 ,  G11C16/0483 ,  G11C16/26 ,  G06F2212/10

Abstract: An information processing apparatus that detects whether the corresponding first element and second element among the multiple first elements and the plurality of second elements are matched or are similar, has one or multiple strings connected to a first wiring and connected to multiple second wirings, wherein the string includes multiple transistor pairs connected in series along a current path having one end connected to the first wiring, each of the multiple transistor pairs includes a first transistor and a second transistor connected in series along the current path, the second wirings are connected to gates of the first transistor and the second transistor in each of the multiple transistor pairs, the first transistor is set to a first threshold depending on first data, the second transistor is set to a second threshold depending on second data that is complement data of the first data.

公开(公告)号：US20240304257A1

公开(公告)日：2024-09-12

申请号：US18590836

申请日：2024-02-28

Applicant: Kioxia Corporation

Inventor： Yuki INUZUKA ,  Hidehiro SHIGA

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/08 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/50 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/50

CPC classification number: G11C16/16 ,  G11C16/0483 ,  G11C16/08 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/50 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/50 ,  G11C2216/02

Abstract: A semiconductor memory device includes first and second semiconductor pillars, a first string including first memory cells connected in series and a second string including second memory cells connected in series on opposite sides of the first semiconductor pillar, respectively, a third string including third memory cells connected in series and a fourth string including fourth memory cells connected in series, on opposite sides of the second semiconductor pillar, respectively, first word lines, second word lines, and a driver configured to supply different voltages to the first and second word lines during an erasing operation to erase data in the second and fourth memory cells. In the erasing operation, the driver supplies a first voltage higher than a reference voltage to the first word lines, and supplies the reference voltage to the second word lines.

公开(公告)号：US20230065167A1

公开(公告)日：2023-03-02

申请号：US17681680

申请日：2022-02-25

Applicant: KIOXIA CORPORATION

Inventor： Tomoki CHIBA ,  Daisaburo TAKASHIMA ,  Hidehiro SHIGA

IPC: G11C13/00

Abstract: A nonvolatile memory includes a first memory cell and a second memory cell above the first memory cell. The first memory cell includes a variable resistance layer extending in a first direction, a semiconductor layer extending in the first direction and in contact with the variable resistance layer, an insulator layer extending in the first direction and in contact with the semiconductor layer, and a first voltage applying electrode extending in a second direction and in contact with the insulator layer. The second memory cell includes a second voltage applying electrode in contact with the insulator layer. When a write operation is performed on the first memory cell, a first voltage is applied to the second voltage applying electrode, and when a write operation is performed on the second memory cell, a second voltage, lower than the first voltage, is applied to the first voltage applying electrode.

公开(公告)号：US20240244839A1

公开(公告)日：2024-07-18

申请号：US18435113

申请日：2024-02-07

Applicant: Kioxia Corporation

Inventor： Kazutaka IKEGAMI ,  Hidehiro SHIGA ,  Shingo NAKAZAWA

IPC: H10B41/35 ,  H10B41/27 ,  H10B41/47

CPC classification number: H10B41/35 ,  H10B41/27 ,  H10B41/47

Abstract: A memory system for low power consumption and high speed read operation in the memory system includes a source line, a string select line having i layers, a first word line having i layers, a second word line having i layers, a select gate line having 1 layer which is divided into 2n, a plurality of memory pillars and a control circuit. Each of the plurality of memory pillars includes a first string and a second string. The first string includes a first transistor, i first memory cells and j second memory cells. The first transistor, the i first memory cells, and the j second memory cells are electrically connected in series. The second string includes a second transistor, i third memory cells, and j fourth memory cells. The second transistor, the i third memory cells, and the j fourth memory cells are electrically connected in series.

公开(公告)号：US20240071477A1

公开(公告)日：2024-02-29

申请号：US18500478

申请日：2023-11-02

Applicant: Kioxia Corporation

Inventor： Kazutaka IKEGAMI ,  Rieko FUNATSUKI ,  Nobuyuki MOMO ,  Hidehiro SHIGA

IPC: G11C11/4096 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4099

CPC classification number: G11C11/4096 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4099

Abstract: A memory system for speeding up a read operation in the memory system includes a first pillar, a first string including a first transistor and a first memory cell, a second string including a second transistor and a second memory cell, a first bit line, a first gate line, a first word line, a second gate line, a second word line and a control circuit. When the control circuit executes a read operation with respect to the first memory cell, the control circuit is configured to apply a read voltage to the first word line, apply a voltage turning off the second memory cell regardless of an electric charge stored in the second memory cell to the second word line, apply a voltage turning on the first transistor to the first gate line, and apply a voltage turning on the second transistor to the second gate line.

公开(公告)号：US20240049479A1

公开(公告)日：2024-02-08

申请号：US18177064

申请日：2023-03-01

Applicant: Kioxia Corporation

Inventor： Yuki ITO ,  Daisaburo TAKASHIMA ,  Hidehiro SHIGA ,  Yoshiki KAMATA

IPC: H10B63/00 ,  H10B61/00

CPC classification number: H10B63/845 ,  H10B63/34 ,  H10B61/22

Abstract: A variable resistance non-volatile memory includes a memory cell including a core portion extending in a first direction above a semiconductor substrate, a variable resistance layer extending in a first direction and in contact with the core portion, a semiconductor layer extending in a first direction and in contact with the variable resistance layer, an insulator layer extending in a first direction and in contact with the semiconductor layer, and a first voltage application electrode extending in a second direction crossing the first direction and in contact with the insulator layer. An impurity concentration of the semiconductor layer is non-uniform, such that an impurity concentration of a first portion of the semiconductor layer in contact with the insulator layer is at least ten times higher than an impurity concentration of a second portion of the semiconductor layer in contact with the variable resistance layer.

公开(公告)号：US20230395167A1

公开(公告)日：2023-12-07

申请号：US18179505

申请日：2023-03-07

Applicant: Kioxia Corporation

Inventor： Takumi FUJIMORI ,  Tetsuya SUNATA ,  Masanobu SHIRAKAWA ,  Hidehiro SHIGA

IPC: G11C16/34 ,  G11C16/16

CPC classification number: G11C16/3445 ,  G11C16/16

Abstract: According to an embodiment, a memory system includes: a nonvolatile memory including a plurality of blocks; and a memory controller. The memory controller is configured to: make a comparison between a first erase voltage application accumulated time period and a first erase verify permission time period each corresponding to a first block targeted for erasure; cause the nonvolatile memory to execute a erase voltage application operation in a case where the first erase voltage application accumulated time period is less than the first erase verify permission time period; and cause the nonvolatile memory to execute a erase verify operation in a case where the first erase voltage application accumulated time period is equal to or greater than the first erase verify permission time period.