公开(公告)号：US11417600B2

公开(公告)日：2022-08-16

申请号：US17079952

申请日：2020-10-26

Applicant: KIOXIA CORPORATION

Inventor： Kosuke Yanagidaira ,  Chikaaki Kodama

IPC: H01L23/528 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/02 ,  H01L23/48

Abstract: A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.

公开(公告)号：US11978508B2

公开(公告)日：2024-05-07

申请号：US18054746

申请日：2022-11-11

Applicant: Kioxia Corporation

Inventor： Kosuke Yanagidaira ,  Hiroshi Tsubouchi ,  Takeshi Hioka

IPC: G11C11/00 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C11/5642 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  H10B41/27 ,  H10B43/27

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a word line, a bit line, a first transistor, a second transistor and a driver. The word line is electrically coupled to a gate of the memory cell. The bit line is electrically coupled to one end of the memory cell. The first transistor includes a first gate electrically coupled to the bit line. The second transistor is coupled to a first end of the first transistor. The driver is configured to apply a voltage to the first gate of the first transistor. In a read operation, the driver varies a voltage to be applied to the first gate of the first transistor based on a read voltage applied to the word line.

公开(公告)号：US11381425B2

公开(公告)日：2022-07-05

申请号：US17125830

申请日：2020-12-17

Applicant: KIOXIA CORPORATION

Inventor： Kensuke Yamamoto ,  Kosuke Yanagidaira

IPC: H04L25/02 ,  G11C29/02 ,  G11C11/4093 ,  G11C7/10 ,  G11C11/16 ,  G11C11/409 ,  H03K19/00 ,  H03K19/17764

Abstract: A semiconductor device includes a first chip and a second chip. The first chip includes a first circuit having a first output terminal. The second chip includes a second circuit having a second output terminal, which is electrically connected to the first output terminal via a first signal line. When the first chip and the second chip receive a first command, the second circuit calibrates an output impedance at the second output terminal through a first calibration operation based on an output impedance at the first output terminal.

公开(公告)号：US12165711B2

公开(公告)日：2024-12-10

申请号：US18228166

申请日：2023-07-31

Applicant: Kioxia Corporation

Inventor： Kosuke Yanagidaira ,  Hiroshi Tsubouchi

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/32 ,  H10B43/10 ,  H10B43/27

Abstract: A semiconductor memory device includes a memory cell connected between a bit line and a source line, a sense amplifier having a first transistor provided between at least two transistors of the sense amplifier and the bit line, and a controller which executes a read operation to read data stored by the memory cell. In the read operation, the controller applies a first voltage to the first transistor and a second voltage to the source line during a first time period, applies a third voltage to the first transistor and a fourth voltage to the source line during a second time period after the first time period, and applies the first voltage to the first transistor and a fifth voltage to the source line during a third time period after the second time period.

公开(公告)号：US11694746B2

公开(公告)日：2023-07-04

申请号：US17184980

申请日：2021-02-25

Applicant: KIOXIA CORPORATION

Inventor： Kosuke Yanagidaira

IPC: G11C11/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  H01L25/065 ,  G11C16/34 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C11/5628 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3459 ,  H01L25/0657 ,  H01L2225/06506 ,  H01L2225/06562 ,  H10B41/27 ,  H10B43/27

Abstract: A semiconductor storage device includes a memory transistor and a word line connected to a gate electrode of the memory transistor. When a write sequence is interrupted before a k+1th verification operation is ended after a kth verification operation is ended in the nth write loop of the write sequence, a voltage equal to or higher than a verification voltage corresponding to a first verification operation in the nth write loop is supplied to the word line before start of the k+1th verification operation after resumption of the write sequence. A time from the resumption of the write sequence to the start of the k+1th verification operation is shorter than a time from start of the first verification operation to end of the kth verification operation in the nth write loop.

公开(公告)号：US11562795B2

公开(公告)日：2023-01-24

申请号：US17363005

申请日：2021-06-30

Applicant: KIOXIA CORPORATION

Inventor： Kosuke Yanagidaira ,  Hiroshi Tsubouchi

IPC: G11C16/26 ,  G11C16/32 ,  G11C16/04 ,  H01L27/11582 ,  H01L27/11565 ,  G11C16/08

Abstract: A semiconductor memory device includes a controller which executes a read operation. In the read operation, the controller applies first and second read voltages to a word line, reads data at each of first and second times, applies the first voltage to a source line at each of the first and second times, applies a second voltage to the source line during the application of the first read voltage to the word line and before the first time, and applies a third voltage to the source line during the application of the second read voltage to the word line and before the second time.

公开(公告)号：US11527284B2

公开(公告)日：2022-12-13

申请号：US17198375

申请日：2021-03-11

Applicant: Kioxia Corporation

Inventor： Kosuke Yanagidaira ,  Hiroshi Tsubouchi ,  Takeshi Hioka

IPC: G11C11/00 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26 ,  G11C16/08 ,  H01L27/11582 ,  H01L27/11556

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a word line, a bit line, a first transistor, a second transistor and a driver. The word line is electrically coupled to a gate of the memory cell. The bit line is electrically coupled to one end of the memory cell. The first transistor includes a first gate electrically coupled to the bit line. The second transistor is coupled to a first end of the first transistor. The driver is configured to apply a voltage to the first gate of the first transistor. In a read operation, the driver varies a voltage to be applied to the first gate of the first transistor based on a read voltage applied to the word line.

公开(公告)号：US11423980B2

公开(公告)日：2022-08-23

申请号：US17184246

申请日：2021-02-24

Applicant: KIOXIA CORPORATION

Inventor： Yuki Shimizu ,  Kosuke Yanagidaira

IPC: G11C16/26 ,  G11C11/56 ,  G11C16/04 ,  H01L27/11582 ,  H01L27/11556

Abstract: A semiconductor storage device includes a first plane storing user data and system information, a second plane storing the user data and the system information, a first latch circuit storing even-numbered bit data of the system information read from the first plane, a second latch circuit storing odd-numbered bit data of the system information read from the second plane, and a sequencer. The sequencer executes in parallel a first process of reading out the even-numbered bit data of the system information from the first plane and storing the read data in the first latch circuit and a second process of reading out the odd-numbered bit data of the system information from the second plane and storing the read data in the second latch circuit.

公开(公告)号：USRE49164E1

公开(公告)日：2022-08-09

申请号：US16842237

申请日：2020-04-07

Applicant: Kioxia Corporation

Inventor： Kosuke Yanagidaira ,  Kazuhide Yoneya

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/06 ,  H01L27/02 ,  H01L21/8238

Abstract: According to one embodiment, a semiconductor device includes a first element isolating area, a first element area surrounding the first element isolating area, a second element isolating area surrounding the first element area a first gate electrode provided on and across the first element isolating area, the first element area, and the second element isolating area, and a second gate electrode isolated from the first gate electrode and provided on and across the first element isolating area, the first element area, and the second element isolating area.

公开(公告)号：US11302399B2

公开(公告)日：2022-04-12

申请号：US17008337

申请日：2020-08-31

Applicant: KIOXIA CORPORATION

Inventor： Kosuke Yanagidaira ,  Takuyo Kodama ,  Takeshi Hioka

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/08 ,  G11C16/04 ,  H01L27/115

Abstract: A semiconductor storage device includes first and second memory cells, first and second word lines connected to the first and second memory cells, respectively, a bit line connected to the first and second memory cells, and a sense amplifier including a sense node. During a first read, a controller applies a first read voltage to the second word line and determines a read result. During a second read, the controller discharges the sense node for a first time period while applying a second read voltage to the first word line to determine a first read result, and discharges the sense node for a second time period while applying the second read voltage to determine a second read result. The controller determines read data based on the first read result, the second read result, and the read result of the second memory cell.