公开(公告)号：US20250031367A1

公开(公告)日：2025-01-23

申请号：US18905560

申请日：2024-10-03

Applicant: KIOXIA CORPORATION

Inventor： Takuya INATSUKA ,  Tadashi IGUCHI ,  Murato KAWAI ,  Hisashi KATO ,  Megumi ISHIDUKI

IPC: H10B43/10 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/50 ,  H10B43/27 ,  H10B43/35 ,  H10B43/50

Abstract: According to one embodiment, a semiconductor memory device includes a first conductive layer, a first semiconductor body, a second semiconductor body, a first memory layer, and a second memory layer. The first conductive layer includes first to fourth extension regions, and a first connection region. The first extension region extends in a first direction. The second extension region extends in the first direction and is arranged with the first extension region in the first direction. The third extension region extends in the first direction and is arranged with the first extension region in a second direction crossing the first direction. The fourth extension region extends in the first direction, is arranged with the third extension region in the first direction, and is arranged with the second extension region in the second direction.

公开(公告)号：US20240365549A1

公开(公告)日：2024-10-31

申请号：US18766417

申请日：2024-07-08

Applicant: KIOXIA CORPORATION

Inventor： Yoshiaki FUKUZUMI ,  Ryota KATSUMATA ,  Masaru KIDOH ,  Masaru KITO ,  Hiroyasu TANAKA ,  Yosuke KOMORI ,  Megumi ISHIDUKI ,  Hideaki AOCHI

IPC: H10B43/27 ,  G11C16/04 ,  H01L29/51 ,  H10B41/20 ,  H10B41/27 ,  H10B43/20 ,  H10B43/40 ,  H10B43/50 ,  H10B99/00

CPC classification number: H10B43/27 ,  G11C16/0483 ,  H01L29/513 ,  H10B41/27 ,  H10B43/20 ,  H10B43/40 ,  H10B43/50 ,  H10B99/00 ,  H10B41/20

Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.

公开(公告)号：US20240057330A1

公开(公告)日：2024-02-15

申请号：US18493933

申请日：2023-10-25

Applicant: KIOXIA CORPORATION

Inventor： Megumi ISHIDUKI

IPC: H10B43/20 ,  H10B41/10 ,  H10B41/20 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/20 ,  H10B41/10 ,  H10B41/20 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: According to one embodiment, a semiconductor memory device includes a stacked layer body including conductive layers stacked to be apart from each other in a first direction, and including a stair-like end with rising parts and terrace parts, wherein successive first conductive layers including an uppermost conductive layer function as select gate lines for a NAND string, and a first contact connected to the uppermost conductive layer provided to correspond to a first rising part which is an uppermost one of the rising parts. The first contact passes through the uppermost conductive layer to be further connected to a first conductive layer adjacent to the uppermost conductive layer.

公开(公告)号：US20240008276A1

公开(公告)日：2024-01-04

申请号：US18465223

申请日：2023-09-12

Applicant: KIOXIA CORPORATION

Inventor： Yoshiaki FUKUZUMI ,  Ryota KATSUMATA ,  Masaru KITO ,  Masaru KIDOH ,  Hiroyasu TANAKA ,  Yosuke KOMORI ,  Megumi ISHIDUKI ,  Junya MATSUNAMI ,  Tomoko FUJIWARA ,  Hideaki AOCHI ,  Ryouhei KIRISAWA ,  Yoshimasa MIKAJIRI ,  Shigeto OOTA

IPC: H10B43/27 ,  H01L29/66 ,  H01L29/792 ,  H10B43/20 ,  H01L21/223 ,  H01L21/265 ,  H01L29/78 ,  H01L29/04 ,  H01L29/16 ,  H01L29/423 ,  H01L29/49 ,  H01L29/10

CPC classification number: H10B43/27 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926 ,  H10B43/20 ,  H01L21/223 ,  H01L21/265 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/04 ,  H01L29/16 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/1037

Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.

公开(公告)号：US20230085271A1

公开(公告)日：2023-03-16

申请号：US17654443

申请日：2022-03-11

Applicant: Kioxia Corporation

Inventor： Megumi ISHIDUKI

IPC: H01L23/528 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/535

Abstract: According to one embodiment, a semiconductor device includes a stacked body in which a plurality of conductive layers including upper conductive layers and lower conductive layers are stacked to be apart from each other in a first direction, and which includes a stairs-shaped end portion, the upper conductive layers functioning as select gate lines for a NAND string, and the lower conductive layers functioning as word lines for the NAND string, a plurality of pillar structures each including a semiconductor layer extending in the first direction through the stacked body, and a first contact connected to two or more first upper conductive layers stacked successively, and provided to extend over upper surfaces of the two or more first upper conductive layers.

公开(公告)号：US20220285509A1

公开(公告)日：2022-09-08

申请号：US17825542

申请日：2022-05-26

Applicant: Kioxia Corporation

Inventor： Megumi ISHIDUKI ,  Hiroshi NAKAKI ,  Takamasa ITO

IPC: H01L29/423 ,  H01L29/66 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/11565 ,  H01L29/792

Abstract: A semiconductor device includes a base body, a stacked body on the base body and a first columnar part. The base body includes a substrate, a first insulating film on the substrate, a first conductive film on the first insulating film, and a first semiconductor part on the first conductive film. The stacked body includes conductive layers and insulating layers stacked alternately in a stacking direction. The first columnar part is provided inside the stacked body and the first semiconductor part. The first columnar part includes a semiconductor body and a memory film between the semiconductor body and conductive layers. The semiconductor body extends in the stacking direction. The first columnar part has a first diameter and a second diameter in a first direction crossing the stacking direction. The first diameter inside the first semiconductor part is larger than the second diameter inside the stacked body.