公开(公告)号：US11495543B2

公开(公告)日：2022-11-08

申请号：US17004234

申请日：2020-08-27

Applicant: Kioxia Corporation

Inventor： Tetsuaki Utsumi

IPC: H01L23/535 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L21/768 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/522 ,  H01L27/11565

Abstract: A semiconductor device includes a substrate and a first semiconductor layer and a second semiconductor layer each extending in a first direction perpendicular to a surface of the substrate. Furthermore, the semiconductor device includes a first plug provided on the first semiconductor layer and a second plug provided on the second semiconductor layers, and a connection wiring having an upper surface that is at a same height along the first direction as upper surfaces of the first and second plugs, and having a lower surface that is at a same height along the first direction as lower surfaces of the first and second plugs. Furthermore, the semiconductor device includes a first wiring provided on the first plug and the connection wiring and a second wiring provided on the second plug and the connection wiring.

公开(公告)号：US11127441B1

公开(公告)日：2021-09-21

申请号：US17010569

申请日：2020-09-02

Applicant: KIOXIA CORPORATION

Inventor： Tetsuaki Utsumi

IPC: G11C7/10 ,  G11C5/06 ,  G11C11/4074 ,  G11C11/408

Abstract: A semiconductor storage device includes a first input driver configured to receive a first signal from a memory controller, a second input driver configured to receive a chip enable signal from the memory controller, and a first control circuit. The first control circuit is configured to set the semiconductor storage device in an enabled state or a disabled state depending on whether or not the first signal which is received during a time period that starts with assertion of the chip enable signal and is prior to receipt of a command sequence, corresponds to a first chip address.

公开(公告)号：US12062704B2

公开(公告)日：2024-08-13

申请号：US18452965

申请日：2023-08-21

Applicant: KIOXIA CORPORATION

Inventor： Tetsuaki Utsumi

IPC: H01L29/423

CPC classification number: H01L29/42324 ,  H01L29/4234

Abstract: A semiconductor memory device includes: a semiconductor substrate; a memory cell array disposed separately from the semiconductor substrate in a first direction; and first and second transistor arrays disposed on the semiconductor substrate. The semiconductor substrate includes a first region to a fourth region arranged in a second direction and a fifth region to an eighth region arranged in the second direction. These regions are each adjacent in a third direction. The memory cell array includes first conducting layers disposed in the first to fourth regions and second conducting layers disposed in the fifth to eighth regions. The first transistor array includes transistors connected to the plurality of first conducting layers via contacts disposed in the second region. The second transistor array includes transistors connected to the plurality of second conducting layers via contacts disposed in the seventh region.

公开(公告)号：US11756634B2

公开(公告)日：2023-09-12

申请号：US17950306

申请日：2022-09-22

Applicant: Kioxia Corporation

Inventor： Tetsuaki Utsumi

IPC: G11C16/30 ,  G11C16/08 ,  G11C16/26 ,  G11C16/24 ,  H10B41/10 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

CPC classification number: G11C16/30 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  H10B41/10 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor memory device includes word lines, first and second select gate lines, first and second semiconductor columns, first and second bit lines, and first and second transistors. The word lines are arranged in a first direction. The first and second select gate lines extend in a second direction and overlap with the word lines viewed from the first direction. The first and second select gate lines are arranged in the second direction. The first semiconductor column is opposed to the word lines and the first select gate line. The second semiconductor column is opposed to the word lines and the second select gate line. The first and second bit lines extend in a third direction and overlap with the first and second semiconductor columns viewed from the first direction. The first and second transistors are electrically connected to the first and second select gate lines.

公开(公告)号：US11710727B2

公开(公告)日：2023-07-25

申请号：US17003694

申请日：2020-08-26

Applicant: KIOXIA CORPORATION

Inventor： Nobuaki Okada ,  Tetsuaki Utsumi

IPC: H01L25/18 ,  H01L23/00 ,  G11C16/30 ,  G11C16/04

CPC classification number: H01L25/18 ,  G11C16/30 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  G11C16/0483 ,  H01L2224/03452 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/08145 ,  H01L2224/09133 ,  H01L2224/09134 ,  H01L2224/09177 ,  H01L2224/09181 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor storage device includes first and second chips and first and second power supply electrodes. The first chip includes conductive layers arranged in a first direction, a semiconductor pillar extending in the first direction and facing the conductive layers, first contacts extending in the first direction and connected to the conductive layers, second contacts extending in the first direction and connected to a first power supply electrode, third contacts extending in the first direction, facing the second contacts in a direction crossing the first direction, and connected to the second power supply electrode, and first bonding electrodes connected to the first contacts. The second chip includes a semiconductor substrate, transistors provided on the semiconductor substrate, fourth contacts connected to the transistors, and second bonding electrodes connected to the fourth contacts. The first and second chips are bonded together so that respective first and second bonding electrodes are connected together.

公开(公告)号：US11538791B2

公开(公告)日：2022-12-27

申请号：US16802462

申请日：2020-02-26

Applicant: KIOXIA CORPORATION

Inventor： Hiroshi Maejima ,  Toshifumi Hashimoto ,  Takashi Maeda ,  Masumi Saitoh ,  Tetsuaki Utsumi

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00

Abstract: A semiconductor memory device includes a memory chip. The memory chip includes a first region including a plurality of first memory cells and second memory cells, a second region different from the first region, a plurality of first word lines stacked apart from each other in a first direction in the first and second regions, a first pillar including a first semiconductor layer extending through the first word lines, and a first insulator layer provided between the first semiconductor layer and the first word lines, in the first region, the first memory cells being located at intersections of the first pillar with the first word lines, a first bonding pad in the second region, and a first transistor between the first word lines and the first bonding pad, and connected between one of the first word lines and the first bonding pad, in the second region.

公开(公告)号：US11121227B2

公开(公告)日：2021-09-14

申请号：US17013286

申请日：2020-09-04

Applicant: Kioxia Corporation

Inventor： Tetsuaki Utsumi

IPC: H01L29/423

Abstract: A semiconductor memory device includes: a semiconductor substrate; a memory cell array disposed separately from the semiconductor substrate in a first direction; and first and second transistor arrays disposed on the semiconductor substrate. The semiconductor substrate includes a first region to a fourth region arranged in a second direction and a fifth region to an eighth region arranged in the second direction. These regions are each adjacent in a third direction. The memory cell array includes first conducting layers disposed in the first to fourth regions and second conducting layers disposed in the fifth to eighth regions. The first transistor array includes transistors connected to the plurality of first conducting layers via contacts disposed in the second region. The second transistor array includes transistors connected to the plurality of second conducting layers via contacts disposed in the seventh region.