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公开(公告)号：US20220084609A1
公开(公告)日：2022-03-17
申请号：US17201332
申请日：2021-03-15
Applicant: Kioxia Corporation
Inventor： Akiyuki MURAYAMA , Kikuko SUGIMAE , Katsuya NISHIYAMA , Motohiko FUJIMATSU , Noboru SHIBATA
Abstract: A semiconductor memory device includes first and second memory string including first and second memory cell, respectively, and first and second bit line connected to first and second memory string, respectively. In a first program operation, a first bit line voltage is supplied to the first and the second bit line. In a second program operation, a second bit line voltage larger than the first bit line voltage or a third bit line voltage larger than the second bit line voltage is supplied to the first and the second bit line. In a third program operation, the second and the third bit line voltage is supplied to the first and the second bit line, respectively. In a fourth program operation, the third and the second bit line voltage is supplied to the first and the second bit line, respectively.
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公开(公告)号：US20200211655A1
公开(公告)日：2020-07-02
申请号：US16724100
申请日：2019-12-20
Applicant: KIOXIA CORPORATION
Inventor： Noboru SHIBATA , Hironori UCHIKAWA , Taira SHIBUYA
Abstract: A semiconductor memory according to an embodiment includes first and second memory cells, first and second memory cell arrays, first and second word lines, and controller. The first and second memory cell array include the first and second memory cells, respectively. The first and second word lines are coupled to the first and second memory cells, respectively. Data of six or more bits including a first bit, a second bit, a third bit, a fourth bit, a fifth bit, and a sixth bit is stored with the use of a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell.
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公开(公告)号：US20230282276A1
公开(公告)日：2023-09-07
申请号：US18196263
申请日：2023-05-11
Applicant: Kioxia Corporation
Inventor： Noboru SHIBATA , Tokumasa HARA
CPC classification number: G11C11/5628 , G11C11/5642 , G11C16/08 , G11C16/26 , G11C16/10 , G11C16/32 , G11C16/3459 , G06F13/16 , G11C16/0483 , G11C2211/5648
Abstract: A semiconductor memory device includes a first memory cell for storing data using at least three levels of threshold voltages, including a first level, a second level higher than the first level and a third level higher than the second level. A first word line is connected to the first memory cell. In writing of data to the first memory cell from a state where a threshold voltage of the first memory cell is the first level, a plurality of program operations and verify operations are performed, each program operation including applying a program voltage to the first word line, each verify operation including applying a read voltage lower than the program voltage. The program operations include a program operation for the second level and a program operation for the third level, and the verify operations include a verify operation for the second level, and do not include a verify operation for the third level.
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公开(公告)号：US20230238059A1
公开(公告)日：2023-07-27
申请号：US18295504
申请日：2023-04-04
Applicant: KIOXIA CORPORATION
Inventor： Tokumasa HARA , Noboru SHIBATA
CPC classification number: G11C11/5628 , G11C16/0483 , G11C16/14 , G06F3/0679 , G06F11/1068 , G06F3/0619 , G06F3/0659 , G11C16/10
Abstract: A memory system includes a nonvolatile memory which comprises a plurality of memory cells capable of storing 4-bit data represented by first to fourth bits by sixteen threshold regions, and a memory controller configured to cause the nonvolatile memory to execute a first program for writing data of the first bit, the second bit, and the fourth bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit. In fifteen boundaries existing between adjacent threshold regions among the first to sixteenth threshold regions, a maximum value of the number of first boundaries used for determining a value of the data of the first bit, the number of second boundaries used for determining a value of the data of the second bit, the number of third boundaries used for determining a value of the data of the third bit.
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公开(公告)号：US20220157387A1
公开(公告)日：2022-05-19
申请号：US17471810
申请日：2021-09-10
Applicant: Kioxia Corporation
Inventor： Tokumasa HARA , Noboru SHIBATA
Abstract: According to one embodiment, a semiconductor memory includes: a memory group including a plurality of memory cells configured to store a plurality of bits of data in three or more plurality of states; a word line coupled to the plurality of memory cells; and a first circuit configured to convert one external address received from an external controller into a plurality of internal addresses, wherein a first page size of page data of the memory group is smaller than a second page
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Patent Agency Ranking
公开(公告)号：US20220148651A1
公开(公告)日：2022-05-12
申请号：US17582330
申请日：2022-01-24
Applicant: Kioxia Corporation
Inventor： Tokumasa HARA , Noboru SHIBATA
Abstract: A memory system has a nonvolatile memory which comprises memory cells capable of storing 4-bit data of first to fourth bits by sixteen threshold regions including a first threshold region corresponding to an erased state and second to sixteenth threshold regions having higher voltage levels than a voltage level of the first threshold region corresponding to a written state; and a controller which causes the nonvolatile memory to execute a first program for writing data of the first bit and the second bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit and the fourth bit. The controller controls such that the threshold region is any threshold region of a seventeenth threshold region corresponding to an erased state and eighteenth to twentieth threshold regions having higher voltage levels than that of the seventeenth threshold region corresponding to a written state.
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公开(公告)号：US20210158867A1
公开(公告)日：2021-05-27
申请号：US17016765
申请日：2020-09-10
Applicant: Kioxia Corporation
Inventor： Tokumasa HARA , Noboru SHIBATA
Abstract: A memory system includes a nonvolatile memory which comprises a plurality of memory cells capable of storing 4-bit data represented by first to fourth bits by sixteen threshold regions, and a memory controller configured to cause the nonvolatile memory to execute a first program for writing data of the first bit, the second bit, and the fourth bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit. In fifteen boundaries existing between adjacent threshold regions among the first to sixteenth threshold regions, a maximum value of the number of first boundaries used for determining a value of the data of the first bit, the number of second boundaries used for determining a value of the data of the second bit, the number of third boundaries used for determining a value of the data of the third bit.
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公开(公告)号：US20210082497A1
公开(公告)日：2021-03-18
申请号：US17014293
申请日：2020-09-08
Applicant: Kioxia Corporation
Inventor： Tokumasa HARA , Noboru SHIBATA
Abstract: A memory system has a nonvolatile memory which comprises memory cells capable of storing 4-bit data of first to fourth bits by sixteen threshold regions including a first threshold region corresponding to an erased state and second to sixteenth threshold regions having higher voltage levels than a voltage level of the first threshold region corresponding to a written state; and a controller which causes the nonvolatile memory to execute a first program for writing data of the first bit and the second bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit and the fourth bit. The controller controls such that the threshold region is any threshold region of a seventeenth threshold region corresponding to an erased state and eighteenth to twentieth threshold regions having higher voltage levels than that of the seventeenth threshold region corresponding to a written state.
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公开(公告)号：US20240339160A1
公开(公告)日：2024-10-10
申请号：US18746964
申请日：2024-06-18
Applicant: Kioxia Corporation
Inventor： Tokumasa HARA , Noboru SHIBATA
CPC classification number: G11C16/26 , G11C16/08 , G11C16/102 , G11C16/30 , G11C16/3404
Abstract: According to one embodiment, a semiconductor memory includes: a memory group including a plurality of memory cells configured to store a plurality of bits of data in three or more plurality of states; a word line coupled to the plurality of memory cells; and a first circuit configured to convert one external address received from an external controller into a plurality of internal addresses, wherein a first page size of page data of the memory group is smaller than a second page size of input data corresponding to the external address.
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公开(公告)号：US20240185930A1
公开(公告)日：2024-06-06
申请号：US18527941
申请日：2023-12-04
Applicant: Kioxia Corporation
Inventor： Noboru SHIBATA , Hironori UCHIKAWA
CPC classification number: G11C16/26 , G11C7/08 , G11C8/14 , G11C16/0483 , G11C16/08 , G11C16/10 , H10B43/27 , H10B43/35 , G11C2207/2245
Abstract: According to one embodiment, a semiconductor memory includes a first memory cell array including a plurality of first memory cells; and a second memory cell array including a plurality of second memory cells. Each of threshold voltages of the first memory cells and the second memory cells is set to any of a first threshold voltage, a second threshold voltage higher than the first threshold voltage, and a third threshold voltage higher than the second threshold voltage. Data of three or more bits including a first bit, a second bit, and a third bit is stored using a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell.
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