公开(公告)号：US07868257B2

公开(公告)日：2011-01-11

申请号：US10598134

申请日：2005-03-09

申请人： Taras Kushta ,  Kaoru Narita ,  Hirokazu Tohya ,  Takanori Saeki ,  Tomoyuki Kaneko

发明人： Taras Kushta ,  Kaoru Narita ,  Hirokazu Tohya ,  Takanori Saeki ,  Tomoyuki Kaneko

IPC分类号： H01R12/04 ,  H05K1/11

CPC分类号： H05K1/0222 ,  H05K1/0269 ,  H05K3/429 ,  H05K2201/09536 ,  H05K2201/09618 ,  H05K2201/09718 ,  H05K2201/09809

摘要： A via transmission line for a multilayer printed circuit board (PCB) in which a wave guiding channel is formed by a signal via or a number of signal vias, an assembly of ground vias surrounding the signal via or corresponding number of coupled signal vias, a set of ground plates from conductor layers of the multilayer PCB, and a clearance hole. In this via transmission line, the signal via, or the number of signal vias forms an inner conductive boundary, ground vias and ground plates from conductor layers of the multilayer PCB form an outer conductive boundary, and the clearance hole provides both isolation of the inner conductive boundary from the outer conductive boundary and high-performance broadband operation of the via transmission line by means of the predetermined clearance hole cross-sectional shape and dimensions where the cross-sectional shape of the clearance hole is defined by the arrangement of ground vias in the outer conductive boundary and dimensions of the clearance hole are determined according to a method to minimize frequency-dependent return losses caused by specific corrugations of the outer conductive boundary formed by ground plates in the wave guiding channel of the via transmission line.

摘要翻译： 一种用于多层印刷电路板（PCB）的通孔传输线，其中通过信号通道或多个信号通路形成波导通道，围绕信号通孔或相应数量的耦合信号通孔的接地通孔的组件， 多层PCB的导体层的接地板组以及间隙孔。 在这个通过传输线路中，信号通孔或信号通道的数量形成内部导电边界，从多层PCB的导体层形成的接地孔和接地板形成外部导电边界，并且间隙孔提供内部 通过外部导电边界的导电边界和通孔传输线的高性能宽带操作，借助于预定的间隙孔横截面形状和尺寸，其中间隙孔的横截面形状由接地通孔的布置 根据通过在通孔传输线的波导通道中由接地板形成的外导电边界的特定波纹引起的频率相关的返回损耗的方法来确定间隙孔的外导电边界和尺寸。

公开(公告)号：US07463122B2

公开(公告)日：2008-12-09

申请号：US10558888

申请日：2004-06-01

申请人： Taras Kushta ,  Kaoru Narita ,  Takanori Saeki ,  Tomoyuki Kaneko ,  Hirokazu Tohya

发明人： Taras Kushta ,  Kaoru Narita ,  Takanori Saeki ,  Tomoyuki Kaneko ,  Hirokazu Tohya

IPC分类号： H01P1/04

CPC分类号： H05K1/0222 ,  H01P3/06 ,  H05K1/024 ,  H05K1/0251 ,  H05K3/429 ,  H05K2201/0187 ,  H05K2201/09063 ,  H05K2201/09536 ,  H05K2201/09618 ,  H05K2201/09718 ,  H05K2201/09809

摘要： A compact via transmission line for a printed circuit board having preferred characteristic impedance and capable of miniaturizing the printed circuit board including a multilayer printed circuit board, and extending the frequency range of a via transmission line mounted on the printed circuit board, and a design method of the same. The transmission line has a central conductor forming an inner conductor layer boundary make up a signal via hole, a plurality of via holes arranged around the central conductor form an outer conductor layer boundary, and a plurality of conductor plates formed of a printed circuit board conductor layer, is further provided with a constitutive parameter adjustment clearance hole between the inner and outer conductor layer boundaries of the compact via transmission line, and electrically isolates to prevent cross-talk of a signal propagating through a signal via hole with other signals in a high-frequency signal band.

摘要翻译： 一种用于具有优选特性阻抗并能够使包括多层印刷电路板的印刷电路板小型化并且扩展安装在印刷电路板上的通孔传输线的频率范围的印刷电路板的紧凑型通路传输线，以及设计方法 一样的。 传输线具有形成内导体层边界的中心导体，构成信号通孔，围绕中心导体布置的多个通孔形成外导体层边界，以及由印刷电路板导体形成的多个导体板 通过传输线在压缩体的内部和外部导体层边界之间进一步设置本构参数调整间隙孔，并且电隔离以防止通过信号通孔传播的信号与其他信号在高电平中的串扰 频率信号频带。

公开(公告)号：US5869871A

公开(公告)日：1999-02-09

申请号：US896952

申请日：1997-07-18

申请人： Kaoru Narita

发明人： Kaoru Narita

IPC分类号： H01L21/822 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/04 ,  H01L27/088 ,  H01L29/78 ,  H01L23/62

CPC分类号： H01L27/0251

摘要： In a semiconductor device including a semiconductor substrate, first and second external terminals, a first impurity diffusion region connected to the first external terminal, and second and third impurity diffusion regions forming a MIS transistor, one of the second and third impurity diffusion regions facing the first impurity region is connected to the second external terminal. The distance between the first diffusion region and the MIS transistor is substantially smaller than a certain value compared to conventional device.

摘要翻译： 在包括半导体衬底，第一和第二外部端子的半导体器件中，连接到第一外部端子的第一杂质扩散区域和形成MIS晶体管的第二和第三杂质扩散区域，第二和第三杂质扩散区域中的一个面向 第一杂质区连接到第二外部端子。 与常规器件相比，第一扩散区域和MIS晶体管之间的距离明显小于一定值。

公开(公告)号：US5724219A

公开(公告)日：1998-03-03

申请号：US655188

申请日：1996-05-30

申请人： Kaoru Narita

发明人： Kaoru Narita

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L23/60 ,  H01L27/02 ,  H01L27/06 ,  H02H3/22

CPC分类号： H01L27/0251

摘要： A semiconductor device according to this invention comprises a first power supply (Vcc) wiring, a second power supply (Gnd) wiring, a first, a second and a third protective elements (3-1, 3-2 and 3-3), a first connecting wiring which connects in common one ends of the first, the second and the third protective elements, a second connecting wiring which connects the other ends of the first, the second and the third protective elements, and a third connecting wiring which connects the first connecting wiring and the first power supply wiring. The third connecting wiring has a resistance which is higher than that of the first connecting wiring.

摘要翻译： 根据本发明的半导体器件包括第一电源（Vcc）布线，第二电源（Gnd）布线，第一，第二和第三保护元件（3-1,3-2和3-3）， 连接在第一，第二和第三保护元件的共同一端的第一连接布线，连接第一，第二和第三保护元件的另一端的第二连接布线，以及连接第 第一连接线和第一电源线。 第三连接布线具有高于第一连接布线的电阻。

公开(公告)号：US5717559A

公开(公告)日：1998-02-10

申请号：US686545

申请日：1996-07-26

申请人： Kaoru Narita

发明人： Kaoru Narita

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/60 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H02H9/00

CPC分类号： H01L27/0262 ,  H01L27/0255 ,  H01L27/0288 ,  H01L29/87

摘要： An input/output protection device for protecting an internal circuit of an integrated circuit formed on a P-type substrate, from an electrostatic discharge (ESD), includes a thyristor connected between a terminal connected to the internal circuit and a common wiring conductor. The protection device comprises a N-well formed in the P-type substrate, a first P-type diffused region formed in the N-well and connected to the terminal, a first N-diffused region formed to adjoin the first N-well, a second P-type diffused region formed in close proximity to the first N-type diffused region, and a second N-type diffused region formed in the P-type substrate and connected to the common wiring conductor. An external resistor is connected between the first P-type diffused region and the first N-type diffused region, and another external resistor is connected between the second P-type diffused region and the second N-type diffused region. A diode is constituted of the first N-diffused region and the second P-type diffused region in close proximity to each other, so that the diode has a low parasitic resistance. Thus, when a negative electrostatic pulse is applied to the terminal, the diode allows a forward current to flow from the common wiring conductor to the terminal through a low impedance path including the first resistor, the diode and the second resistor.

摘要翻译： 用于保护形成在P型衬底上的集成电路的内部电路与静电放电（ESD）的输入/输出保护装置包括连接在连接到内部电路的端子和公共布线导体之间的晶闸管。 保护装置包括在P型衬底中形成的N阱，形成在N阱中并连接到端子的第一P型扩散区域，形成为邻接第一N阱的第一N扩散区域， 形成在第一N型扩散区域附近的第二P型扩散区域和形成在P型衬底中并连接到公共布线导体的第二N型扩散区域。 在第一P型扩散区域和第一N型扩散区域之间连接有外部电阻器，在第二P型扩散区域和第二N型扩散区域之间连接有另一个外部电阻器。 二极管由彼此靠近的第一N扩散区域和第二P型扩散区域构成，使得二极管具有低寄生电阻。 因此，当向端子施加负静电脉冲时，二极管允许正向电流通过包括第一电阻器，二极管和第二电阻器的低阻抗路径从公共布线导体流到端子。

公开(公告)号：US5307310A

公开(公告)日：1994-04-26

申请号：US743238

申请日：1991-08-09

申请人： Kaoru Narita

发明人： Kaoru Narita

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78

CPC分类号： H01L27/10823 ,  H01L27/10808 ,  Y10S257/908

摘要： A dynamic random access memory comprises a p-type semiconductor substrate and a plurality of first n-type diffused regions embedded in the substrate so that they extend along a first axis of the substrate parallel with first and second, opposed major surfaces of the substrate to form parallel bit lines. A matrix array of insulated gate electrodes extend along a second axis of the substrate normal to the first axis from the first major surface into the first n-type diffused regions, so that those of the insulated gate electrodes which are arranged along rows of the matrix are connected together by the parallel bit lines. Second n-type diffused regions are embedded in the substrate adjacent to the first major surface as well as to corresponding ones of the insulated gate electrodes. Parallel conductors extend along a third axis of the substrate for electrically connecting those of the gate electrodes which are arranged along columns of the matrix array to respective word lines, the third axis being perpendicular to both of the first and second axes. Capacitors are stacked on the insulated gate electrodes, respectively. Each of the capacitors has a cell electrode coupled to one of the second n-type diffused regions, a common electrode and a charge storage layer interposed therebetween.

摘要翻译： 动态随机存取存储器包括p型半导体衬底和嵌入在衬底中的多个第一n型扩散区域，使得它们沿衬底的第一轴线平行于衬底的第一和第二相对的主表面延伸到 形成并行位线。 绝缘栅电极的矩阵阵列沿着垂直于第一轴的基板的第二轴从第一主表面延伸到第一n型扩散区域，使得绝缘栅电极沿着矩阵行排列的那些 通过并行位线连接在一起。 第二n型扩散区域嵌入在与第一主表面相邻的衬底中以及相应的绝缘栅电极中。 平行导体沿着衬底的第三轴线延伸，用于将沿矩阵阵列的列布置的栅极电极连接到相应的字线，第三轴线垂直于第一和第二轴线。 电容器分别堆叠在绝缘栅电极上。 每个电容器具有耦合到第二n型扩散区域之一的单元电极，介于其间的公共电极和电荷存储层。

公开(公告)号：US5170232A

公开(公告)日：1992-12-08

申请号：US709818

申请日：1991-06-04

申请人： Kaoru Narita

发明人： Kaoru Narita

IPC分类号： H01L27/092 ,  H01L29/78

CPC分类号： H01L27/0922 ,  H01L29/7836 ,  Y10S257/90

摘要： In a n-channel MOS transistor of LDD structure with sidewall spacers, a p-type diffusion layer is formed to be on the surface of a n.sup.- drain layer just underneath the sidewall spacer and to be separated from the channel region. The low impurity concentration drain layer therefore becomes separated from the sidewall spacer, and thus degradation incident to LDD due to injection of hot carriers into the sidewall spacer can be prevented.

摘要翻译： 在具有侧壁间隔物的LDD结构的n沟道MOS晶体管中，p型扩散层形成在刚好在侧壁间隔物下方的n漏极层的表面上并且与沟道区分离。 因此，低杂质浓度漏极层与侧壁间隔物分离，因此可以防止由于将热载流子注入侧壁间隔而入射到LDD的劣化。

公开(公告)号：US08101529B2

公开(公告)日：2012-01-24

申请号：US12526245

申请日：2008-01-18

申请人： Kaoru Narita

发明人： Kaoru Narita

IPC分类号： H01L21/82

CPC分类号： H01L27/0629 ,  B82Y10/00 ,  G11C13/025 ,  G11C17/16 ,  G11C17/165 ,  H01C7/006 ,  H01C17/0652 ,  H01L28/22 ,  H01L29/0665 ,  H01L29/0673 ,  H01L51/0018 ,  H01L51/0048 ,  Y10S977/961

摘要： A process for producing a carbon nanotube resistor that is capable of providing a highly reliable resistor or fuse. The process comprises the step of introducing a carbon nanotube in a volatile solvent to a first concentration and conducting ultrasonic treatment thereof to thereby obtain an initial solution; the dilution step of stepwise diluting the initial solution with a volatile solvent under ultrasonication so as to adjust the same to a second concentration, thereby obtaining a coating solution; and the step of applying the coating solution between a first electrode and a second electrode, wherein the first concentration is 1(E10−4 g/ml or higher and the second concentration lower than 1(E10−5 g/ml.

摘要翻译： 一种能够提供高度可靠的电阻或熔丝的碳纳米管电阻器的制造方法。 该方法包括将挥发性溶剂中的碳纳米管引入第一浓度并进行超声波处理从而获得初始溶液的步骤; 稀释步骤，在超声波处理下用挥发性溶剂逐步稀释初始溶液，以将其调节至第二浓度，从而获得涂布溶液; 以及在第一电极和第二电极之间施加涂布溶液的步骤，其中第一浓度为1（E10-4g / ml或更高，第二浓度低于1（E10-5g / ml）。

公开(公告)号：US20110260293A1

公开(公告)日：2011-10-27

申请号：US13063229

申请日：2009-07-22

申请人： Kaoru Narita

发明人： Kaoru Narita

IPC分类号： H01L29/93 ,  H01L21/20 ,  B82Y99/00 ,  B82Y40/00

CPC分类号： H01G7/06 ,  H01G4/33

摘要： Provided is a variable capacitance device including a nanomaterial layer made of a plurality of kinds of nanomaterials having characteristics different from each other, a first conductive layer electrically connected to at least a part of the nanomaterial layer, and a second conductive layer facing the nanomaterial layer and the first conductive layer through an insulating film.

摘要翻译： 提供一种可变电容器件，其包括由具有彼此不同的特性的多种纳米材料制成的纳米材料层，与纳米材料层的至少一部分电连接的第一导电层和面向纳米材料层的第二导电层 和通过绝缘膜的第一导电层。

公开(公告)号：US08013685B2

公开(公告)日：2011-09-06

申请号：US12281460

申请日：2007-03-02

申请人： Taras Kushta ,  Kaoru Narita ,  Tomoyuki Kaneko ,  Shin-ichi Ogou

发明人： Taras Kushta ,  Kaoru Narita ,  Tomoyuki Kaneko ,  Shin-ichi Ogou

IPC分类号： H03H7/38

CPC分类号： H05K1/116 ,  H05K1/0219 ,  H05K1/0222 ,  H05K1/0245 ,  H05K1/0251 ,  H05K3/429 ,  H05K2201/09381 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2201/09727

摘要： According to one embodiment, a broadband transition to joint a via structure and a planar transmission line in a multilayer substrate is formed as an intermediate connection between the signal via pad and the planar transmission line disposed at the same conductor layer. The transverse dimensions of the transition are equal to the via pad diameter at the one end and strip width at another end; The length of the transition can be equal to the characteristic dimensions of the clearance hole in the direction of the planar transmission line or defined as providing the minimal excess inductive reactance in time-domain according to numerical diagrams obtained by three-dimensional full-wave simulations.

摘要翻译： 根据一个实施例，形成在多层基板中连接通孔结构和平面传输线的宽带转变，作为信号通孔焊盘和布置在相同导体层处的平面传输线之间的中间连接。 过渡的横向尺寸等于一端的通孔焊盘直径和另一端的带宽度; 转换的长度可以等于平面传输线方向上的间隙孔的特征尺寸，或者定义为根据通过三维全波模拟获得的数值图在时域中提供最小的额外的电抗 。