公开(公告)号：US07113060B2

公开(公告)日：2006-09-26

申请号：US10332267

申请日：2001-07-06

申请人： Masaharu Ito ,  Kenichi Maruhashi ,  Keiichi Ohata

发明人： Masaharu Ito ,  Kenichi Maruhashi ,  Keiichi Ohata

IPC分类号： H01P1/208

CPC分类号： H01P1/2088

摘要： A dielectric waveguide tube band-pass filter assuming lower characteristic change upon mounting, and having smaller dimensions and lower loss. Conductor layers (2a, 2c) are formed on the top and bottom surfaces of a dielectric substrate (1), wherein the top conductor layer 2a and the bottom conductor layer 2c are connected together through via-holes (3a). The via-holes (3a) are formed in at least two rows along the signal transfer direction. In the dielectric waveguide tube configured by the top and bottom conductor layers (2a, 2c) and the via-holes (3a), via-holes (3b) are arranged in the signal transfer direction at spacing equal to or below ½ of the in-tube wavelength to thereby configure resonators. The dielectric band-pass filter is configured by coupling adjacent resonators together through the via-holes (3b) configuring inductive windows. On the surface of the dielectric substrate (1), a co-planar line (4) including the conductor layer (2) as the ground and the conductor layer (2b) as a signal conductor is configured so as to overstride the inductive windows configured by the via-holes (3a).

摘要翻译： 介质波导管带通滤波器，其安装时的特性变化较小，尺寸较小，损耗较小。 导体层（2a，2c）形成在电介质基板（1）的顶表面和底表面上，其中顶导体层2a和底导体层2c通过通孔（3a）连接在一起， 。 通孔（3a）沿着信号传送方向至少形成两行。 在由顶部和底部导体层（2a，2c）和通孔（3a）构成的电介质波导管中，通孔（3b）以信号传输方向布置在等于或低于 一半的管内波长，从而配置谐振器。 介质带通滤波器通过将构成感应窗口的通孔（3b）耦合在一起而构成。 在电介质基板（1）的表面上，包括作为接地的导体层（2）和作为信号导体的导体层（2b）的共平面线（4）构成为跨越构成的电感窗 通过通孔（3a）。

公开(公告)号：US20050156688A1

公开(公告)日：2005-07-21

申请号：US10502782

申请日：2003-01-31

申请人： Masaharu Ito ,  Kenichi Maruhashi ,  Keiichi Ohata

发明人： Masaharu Ito ,  Kenichi Maruhashi ,  Keiichi Ohata

IPC分类号： H01P1/208 ,  H01P5/107

CPC分类号： H01P1/2088 ,  H01P5/107

摘要： A conductive layer is formed on each of the upper and lower surfaces of a dielectric substrate, and the two conductive layers are connected by rows of via-holes that are formed which a spacing that is less than or equal to ½ of the wavelength in the dielectric substrate in the resonance frequency, whereby n stages of dielectric resonators and input/output waveguide structures are formed. If the number n of stages is assumed to be 3, the first-stage resonator and the second-stage resonator are coupled by an electromagnetic field by means of via-holes of a first spacing; the second-stage resonator and the third-stage resonator are coupled by an electromagnetic by means of via-holes of a second spacing, whereby a filter is formed. The input/output waveguide structure and the filter are coupled by an electromagnetic by means of via-holes of a fourth spacing. The first-stage resonator and the third-stage resonator are coupled by an electromagnetic field by means of via-holes of a third spacing.

摘要翻译： 在电介质基板的上表面和下表面的每一个上形成导电层，并且两个导电层通过形成的行的通孔连接，所述通孔的间隔小于或等于 电介质基板的谐振频率，从而形成n级介质谐振器和输入/输出波导结构。 如果假设n个级数为3，则第一级谐振器和第二级谐振器通过电磁场通过第一间隔的通孔耦合; 第二级谐振器和第三级谐振器借助于具有第二间隔的通孔的电磁耦合，从而形成滤波器。 输入/输出波导结构和滤波器通过第四间隔通孔的电磁耦合。 第一级谐振器和第三级谐振器通过第三间隔的通孔由电磁场耦合。

公开(公告)号：US06518864B1

公开(公告)日：2003-02-11

申请号：US09525986

申请日：2000-03-15

申请人： Masaharu Ito ,  Kenichi Maruhashi ,  Keiichi Ohata

发明人： Masaharu Ito ,  Kenichi Maruhashi ,  Keiichi Ohata

IPC分类号： H01P308

CPC分类号： H05K1/024 ,  H01L2223/6627 ,  H01L2924/1903 ,  H01P3/003 ,  H05K1/0219 ,  H05K2201/0187 ,  H05K2201/09036 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09618 ,  H05K2201/09627 ,  H05K2201/09709

摘要： The present invention provides a transmission line structure comprising: a dielectric substrate having first and second surfaces; a signal conductive layer selectively provided on the first surface of the dialectic substrate for signal transmission; at least a first non-signal conductive layer being selectively provided on the first surface of the dialectic substrate, and the at least first non-signal conductive layer being separated from the signal conductive layer; and a second non-signal conductive layer being provided on the second surface of the dialectic substrate, wherein the dielectric substrate has at least a conductive region extending in contact with only one of the at least first non-signal conductive layer and the second non-signal conductive layer so that the at least conductive region is separated by the dielectric substrate from remaining one of the first non-signal conductive layers and the second non-signal conductive layer in view of a vertical direction to the first and second surfaces of the dielectric substrate.

摘要翻译： 本发明提供了一种传输线结构，包括：具有第一和第二表面的电介质基片; 选择性地设置在所述辩证基板的第一表面上用于信号传输的信号导电层; 至少第一非信号导电层选择性地设置在辩证基板的第一表面上，并且所述至少第一非信号传导层与信号导电层分离; 第二非信号导电层设置在辩证基板的第二表面上，其中介电基片具有至少一个导电区域，该导电区域仅与至少第一非信号导电层和第二非信号导电层中的仅一个接触， 考虑到与电介质的第一和第二表面垂直的方向，所述至少导电区域被电介质基板与剩余的第一非信号导电层和第二非信号导电层之一分离 基质。

公开(公告)号：US06774748B1

公开(公告)日：2004-08-10

申请号：US09711541

申请日：2000-11-13

申请人： Masaharu Ito ,  Kenichi Maruhashi ,  Kazuhiro Ikuina ,  Keiichi Ohata

发明人： Masaharu Ito ,  Kenichi Maruhashi ,  Kazuhiro Ikuina ,  Keiichi Ohata

IPC分类号： H01L23051

CPC分类号： H01P1/047 ,  H01L23/057 ,  H01L23/49827 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1423 ,  H01L2924/16195 ,  H01L2924/1903 ,  H01L2924/19033 ,  H01L2924/00

摘要： An RF package includes a multilayered dielectric substrate, a feed-through, and metal members. First and second dielectric substrates are formed on the multilayered dielectric substrate. The multilayered dielectric substrate has a cavity where a semiconductor element is to be mounted. The feed-through connects the inside and outside of the cavity and is comprised of a coplanar line formed on the first dielectric substrate and an inner layer line obtained by forming the second dielectric substrate on the coplanar line. The coplanar line and the inner layer line share a strip-like signal conductor. The metal members are formed at a connection interface between the coplanar line and the inner layer line on two sides of the signal conductor.

摘要翻译： RF封装包括多层电介质基板，馈通和金属构件。 第一和第二电介质基板形成在多层电介质基板上。 多层电介质基板具有要安装半导体元件的空腔。 馈通连接空腔的内部和外部，并且包括形成在第一电介质基板上的共面线和通过在共面线上形成第二电介质基板而获得的内层线。 共面线和内层线共享带状信号导体。 金属构件形成在信号导体两侧的共面线和内层线之间的连接界面处。

公开(公告)号：US20090115548A1

公开(公告)日：2009-05-07

申请号：US12088173

申请日：2006-08-29

申请人： Yasuhiro Hamada ,  Keiichi Ohata ,  Kenichi Maruhashi ,  Takao Morimoto ,  Masaharu Itou ,  Shuuya Kishimoto

发明人： Yasuhiro Hamada ,  Keiichi Ohata ,  Kenichi Maruhashi ,  Takao Morimoto ,  Masaharu Itou ,  Shuuya Kishimoto

IPC分类号： H03H11/32 ,  H03H7/42

CPC分类号： H01P5/10

摘要： A balun circuit includes a first CPW line 11, a second CPW line 12a, and a third CPW line 12b that serve as signal input/output ports; a first CPS line 14a that is a differential transmission line, the first CPS line 14a relaying the first CPW line 11 to the second CPW line 12a; a second CPS line 14b that is a differential transmission line, the second CPS line 14b relaying the first CPW line 11 to the third CPW line 12b; and at least one connection section that connects grounded conductors of each of the first CPW line 11, the second CPW line 12a, and the third CPW line 12b.

摘要翻译： 平衡 - 不平衡转换电路包括用作信号输入/输出端口的第一CPW线11，第二CPW线12a和第三CPW线12b; 作为差分传输线的第一CPS线14a，将第一CPW线11中继到第二CPW线12a的第一CPS线14a; 作为差分传输线的第二CPS线14b，将第一CPW线11中继到第三CPW线12b的第二CPS线14b; 以及至少一个连接部分，其连接第一CPW线11，第二CPW线12a和第三CPW线12b中的每一个的接地导体。

公开(公告)号：US07710216B2

公开(公告)日：2010-05-04

申请号：US12088173

申请日：2006-08-29

申请人： Yasuhiro Hamada ,  Keiichi Ohata ,  Kenichi Maruhashi ,  Takao Morimoto ,  Masaharu Itou ,  Shuuya Kishimoto

发明人： Yasuhiro Hamada ,  Keiichi Ohata ,  Kenichi Maruhashi ,  Takao Morimoto ,  Masaharu Itou ,  Shuuya Kishimoto

IPC分类号： H03H7/42 ,  H01P3/08

CPC分类号： H01P5/10

摘要： A balun circuit includes a first CPW line 11, a second CPW line 12a, and a third CPW line 12b that serve as signal input/output ports; a first CPS line 14a that is a differential transmission line, the first CPS line 14a relaying the first CPW line 11 to the second CPW line 12a; a second CPS line 14b that is a differential transmission line, the second CPS line 14b relaying the first CPW line 11 to the third CPW line 12b; and at least one connection section that connects grounded conductors of each of the first CPW line 11, the second CPW line 12a, and the third CPW line 12b.

摘要翻译： 平衡 - 不平衡转换电路包括用作信号输入/输出端口的第一CPW线11，第二CPW线12a和第三CPW线12b; 作为差分传输线的第一CPS线14a，将第一CPW线11中继到第二CPW线12a的第一CPS线14a; 作为差分传输线的第二CPS线14b，将第一CPW线11中继到第三CPW线12b的第二CPS线14b; 以及至少一个连接部分，其连接第一CPW线11，第二CPW线12a和第三CPW线12b中的每一个的接地导体。

公开(公告)号：US06437654B2

公开(公告)日：2002-08-20

申请号：US09195692

申请日：1998-11-19

申请人： Kenichi Maruhashi ,  Keiichi Ohata

发明人： Kenichi Maruhashi ,  Keiichi Ohata

IPC分类号： H01P1387

CPC分类号： H01P1/387 ,  H01L2924/0002 ,  H01L2924/00

摘要： A substrate-type non-reciprocal circuit element comprises a substrate, a ferrite embedded in the substrate, a central electrode formed on the ferrite at one principal surface of the substrate, a plurality of signal conductors formed on the one principal surface of the substrate to extend from the central electrode into a plurality of different outward directions, a first ground electrode formed on the one principal surface of the substrate, separately from the central electrode and the plurality of signal conductors, and a second ground electrode formed on the other principal surface of the substrate and electrically connected to the first ground electrode. Thus, the substrate-type non-reciprocal circuit element can be easily electrically connected to a measurement machine, to enable to precisely and easily measure an electrical characteristics with a good repeatability. In addition, the substrate-type non-reciprocal circuit element can be connected to an electric circuit such as a receiver circuit and a transmitter circuit with a low transmission loss and a low variation in the transmission loss.

摘要翻译： 衬底型不可逆电路元件包括衬底，嵌入衬底中的铁氧体，在衬底的一个主表面上形成在铁氧体上的中心电极，形成在衬底的一个主表面上的多个信号导体， 从所述中心电极延伸到多个不同的向外方向，与所述中心电极和所述多个信号导体分开形成在所述基板的所述一个主表面上的第一接地电极和形成在所述另一个主表面上的第二接地电极 并且电连接到第一接地电极。 因此，基板型不可逆电路元件可以容易地电连接到测量机器，以便能够以良好的重复精度精确且容易地测量电气特性。 此外，基板型不可逆电路元件可以连接到诸如接收器电路的电路和具有低传输损耗和低传输损耗变化的发射机电路。

公开(公告)号：US4903091A

公开(公告)日：1990-02-20

申请号：US197485

申请日：1988-05-23

申请人： Toshio Baba ,  Masaki Ogawa ,  Keiichi Ohata

发明人： Toshio Baba ,  Masaki Ogawa ,  Keiichi Ohata

IPC分类号： H01L29/10 ,  H01L29/43 ,  H01L29/778

CPC分类号： H01L29/1066 ,  H01L29/10 ,  H01L29/432 ,  H01L29/7787

摘要： A heterojunction transistor has a first semiconductor layer of a semi-insulating or a low impurity concentration, a second semiconductor layer formed on the first semiconductor layer and made of such a semiconductor material that, in cooperation with the first semiconductor layer, a first energy recess for electrons and a second energy recess for holes are respectively formed at the bottom of the conduction band and at the top of the valence band to constitute a conductive channel, a third semiconductor layer formed on the second semiconductor layer and forming a PN-junction with the upper surface of the second semiconductor layer to inject carriers into the conductive channel, a control electrode for applying an input signal to the third semiconductor layer, and a ground and an output electrode formed on the second semiconductor layer on the opposite sides of the third semiconductor layer.

摘要翻译： 异质结晶体管具有半绝缘或低杂质浓度的第一半导体层，形成在第一半导体层上并由这种半导体材料制成的第二半导体层，第二半导体层与第一半导体层协作，形成第一能量凹槽 对于电子和用于空穴的第二能量凹槽分别形成在导带的底部和价带的顶部以构成导电通道;第三半导体层，形成在第二半导体层上并形成具有 所述第二半导体层的上表面将载流子注入到所述导电通道中，用于向所述第三半导体层施加输入信号的控制电极，以及形成在所述第三半导体层的相对侧上的所述第二半导体层上的接地和输出电极 半导体层。

公开(公告)号：US4727403A

公开(公告)日：1988-02-23

申请号：US849336

申请日：1986-04-08

申请人： Hikaru Hida ,  Keiichi Ohata

发明人： Hikaru Hida ,  Keiichi Ohata

IPC分类号： H01L29/812 ,  H01L21/338 ,  H01L29/10 ,  H01L29/20 ,  H01L29/205 ,  H01L29/68 ,  H01L29/778 ,  H01L29/80 ,  H01L33/06 ,  H01L33/30 ,  H01L33/40 ,  H01S5/062

CPC分类号： H01L29/1066 ,  H01L29/10 ,  H01L29/7783 ,  H01S5/06203

摘要： A semiconductor device including a first semiconductor layer having a low carrier density, a second semiconductor layer on the first semiconductor layer and having a low carrier density, a third semiconductor layer on the second semiconductor layer, a fourth semiconductor layer on the third semiconductor layer and effective to inject holes into the second semiconductor layer through the third semiconductor layer for inducing a channel of, for example, electrons in the second semiconductor layer in proximity to and along the interface between the second and third semiconductor layers, and a pair of ohmic contact regions extending through the second and third semiconductor layers for providing ohmic contact with the second semiconductor layer for permitting modulation of the conductance between the ohmic contact regions when holes, for example, are injected from the fourth semiconductor layer into the second semiconductor layer. The device has double heterojunctions, one between the first and second semiconductor layers and the other between the second and third semiconductor layers, thus providing FET mode and bipolar mode of operation.

摘要翻译： 一种半导体器件，包括具有低载流子密度的第一半导体层，在第一半导体层上具有低载流子密度的第二半导体层，第二半导体层上的第三半导体层，第三半导体层上的第四半导体层， 有效地通过第三半导体层向第二半导体层注入空穴，用于在第二半导体层中接近并沿着第二和第三半导体层之间的界面诱导例如电子的沟道，以及一对欧姆接触 延伸穿过第二和第三半导体层的区域，用于与第二半导体层提供欧姆接触，以允许例如从第四半导体层向第二半导体层注入空穴时的欧姆接触区域之间的电导的调制。 该器件具有双异质结，一个在第一和第二半导体层之间，另一个在第二和第三半导体层之间，从而提供FET模式和双极工作模式。

公开(公告)号：US4948751A

公开(公告)日：1990-08-14

申请号：US196009

申请日：1988-05-19

申请人： Akihiko Okamoto ,  Keiichi Ohata

发明人： Akihiko Okamoto ,  Keiichi Ohata

IPC分类号： H01L21/203 ,  H01L21/20 ,  H01L21/205

CPC分类号： H01L21/02395 ,  H01L21/02463 ,  H01L21/02488 ,  H01L21/02546 ,  H01L21/02639 ,  H01L21/02661 ,  Y10S148/026 ,  Y10S148/065 ,  Y10S148/097 ,  Y10S148/169 ,  Y10S438/909

摘要： A method of selective epitaxial growth includes a step of selectively forming an insulator film on a predetermined region of a semiconductor substrate and a step of evaporating a starting material containing a Group III element in vacuum in the presence of a Group V element to grow epitaxially a III-V compound semiconductor selectively on the semiconductor substrate under the condition where the partial pressure of the Group III element just above the semiconductor substrate is greater than the equilibrium vapor pressure of the Group III element contained in the III-V compound semiconductor existing on the semiconductor substrate and is smaller than the equilibrium vapor pressure of the Group III element contained in the III-V compound semiconductor existing on the insulator film.When InAs is grown epitaxially and selectively on a GaAs substrate, the GaAs substrate is kept at 500.degree. to 650.degree. C. and when GaAs is grown epitaxially and selectively on the GaAs substrate, the GaAs substrate is kept at 700.degree. to 775.degree. C.

摘要翻译： 选择性外延生长的方法包括在半导体衬底的预定区域上选择性地形成绝缘膜的步骤和在V族元素存在下在真空中蒸发含有III族元素的起始材料以在外延生长的步骤 III-V族化合物半导体在半导体衬底上方的III族元素的分压大于存在于III-V族化合物半导体中的III-V族化合物半导体中的III族元素的平衡蒸气压的条件下， 并且小于存在于绝缘膜上的III-V族化合物半导体中所含的III族元素的平衡蒸气压。 当在GaAs衬底上外延和选择性地生长InAs时，GaAs衬底保持在500至650℃，并且当GaAs在GaAs衬底上外延和选择性地生长GaAs时，GaAs衬底保持在700℃至775℃ 。