专利检索 ap:("Kenneth C. Wu" OR "Eugene A. Fitzgerald" OR "Jeffrey T. Borenstein" OR "Gianna Taraschi") AND inv:"Eugene A. Fitzgerald" 第 2 页

11.

发明申请
MONOLITHICALLY INTEGRATED PHOTODETECTORS 有权
标题翻译：单一集成的光电复印机

公开(公告)号：US20090242935A1

公开(公告)日：2009-10-01

申请号：US11591658

申请日：2006-11-01

申请人： Eugene A. Fitzgerald

发明人： Eugene A. Fitzgerald

IPC分类号： H01L31/0336 , H01L31/00

CPC分类号： H01L27/14601 , H01L21/0245 , H01L21/0251 , H01L21/76254 , H01L21/8258 , H01L27/0605 , H01L27/144 , H01L27/1446 , H01L27/14683 , H01L27/15 , H01L27/156 , H01L31/0328 , H01L31/143 , H01L31/162 , H01L2924/0002 , Y10S438/933 , H01L2924/00

摘要： Methods and structures for monolithically integrating monocrystalline silicon and monocrystalline non-silicon materials and devices are provided. In one structure, a monolithically integrated semiconductor device structure comprises a silicon substrate and a first monocrystalline semiconductor layer disposed over the silicon substrate, wherein the first monocrystalline semiconductor layer has a lattice constant different from a lattice constant of relaxed silicon. The structure further includes an insulating layer disposed over the first monocrystalline semiconductor layer in a first region and a monocrystalline silicon layer disposed over the insulating layer in the first region. The structure includes at least one silicon-based photodetector comprising an active region including at least a portion of the monocrystalline silicon layer. The structure also includes a second monocrystalline semiconductor layer disposed over at least a portion of the first monocrystalline semiconductor layer in a second region and absent from the first region, wherein the second monocrystalline semiconductor layer has a lattice constant different from the lattice constant of relaxed silicon. The structure includes at least one non-silicon photodetector comprising an active region including at least a portion of the second monocrystalline semiconductor layer.

摘要翻译： 提供了单晶硅和单晶非硅材料和器件单片集成的方法和结构。在一种结构中，单片集成半导体器件结构包括硅衬底和设置在硅衬底上的第一单晶半导体层，其中第一单晶半导体层具有与松弛硅的晶格常数不同的晶格常数。该结构还包括设置在第一区域中的第一单晶半导体层上的绝缘层和设置在第一区域中的绝缘层上的单晶硅层。该结构包括至少一个硅基光电检测器，其包括至少部分单晶硅层的有源区。该结构还包括第二单晶半导体层，其设置在第二区域中的第一单晶半导体层的至少一部分上且不存在于第一区域中，其中第二单晶半导体层具有与松弛硅的晶格常数不同的晶格常数。该结构包括至少一个非硅光电检测器，其包括包括第二单晶半导体层的至少一部分的有源区。

12.

发明授权
Monolithically integrated light emitting devices 有权
标题翻译：单片集成发光器件

公开(公告)号：US07535089B2

公开(公告)日：2009-05-19

申请号：US11591657

申请日：2006-11-01

申请人： Eugene A. Fitzgerald

发明人： Eugene A. Fitzgerald

IPC分类号： H01L23/06

CPC分类号： H01L27/14601 , H01L21/0245 , H01L21/0251 , H01L21/76254 , H01L21/8258 , H01L27/0605 , H01L27/144 , H01L27/1446 , H01L27/14683 , H01L27/15 , H01L27/156 , H01L31/0328 , H01L31/143 , H01L31/162 , H01L2924/0002 , Y10S438/933 , H01L2924/00

摘要： Methods and structures for monolithically integrating monocrystalline silicon and monocrystalline non-silicon materials and devices are provided. In one structure, a monolithically integrated semiconductor device structure comprises a silicon substrate and a first monocrystalline semiconductor layer disposed over the silicon substrate, wherein the first monocrystalline semiconductor layer has a lattice constant different from a lattice constant of relaxed silicon. The structure further includes an insulating layer disposed over the first monocrystalline semiconductor layer in a first region and a monocrystalline silicon layer disposed over the insulating layer in the first region. The structure includes at least one silicon-based electronic device including an element including at least a portion of the monocrystalline silicon layer. The structure also includes a second monocrystalline semiconductor layer disposed over at least a portion of the first monocrystalline semiconductor layer in a second region and absent from the first region, wherein the second monocrystalline semiconductor layer has a lattice constant different from the lattice constant of relaxed silicon. The structure includes at least one III-V light-emitting device including an active region including at least a portion of the second monocrystalline semiconductor layer.

摘要翻译： 提供了单晶硅和单晶非硅材料和器件单片集成的方法和结构。在一种结构中，单片集成半导体器件结构包括硅衬底和设置在硅衬底上的第一单晶半导体层，其中第一单晶半导体层具有与松弛硅的晶格常数不同的晶格常数。该结构还包括设置在第一区域中的第一单晶半导体层上的绝缘层和设置在第一区域中的绝缘层上的单晶硅层。该结构包括至少一个硅基电子器件，其包括至少部分单晶硅层的元件。该结构还包括第二单晶半导体层，其设置在第二区域中的第一单晶半导体层的至少一部分上且不存在于第一区域中，其中第二单晶半导体层具有与松弛硅的晶格常数不同的晶格常数。该结构包括至少一个III-V发光器件，其包括包括第二单晶半导体层的至少一部分的有源区。

13.

发明授权
Buried-channel devices and substrates for fabrication of semiconductor-based devices 有权
标题翻译：用于制造基于半导体的器件的掩埋沟道器件和衬底

公开(公告)号：US06838728B2

公开(公告)日：2005-01-04

申请号：US10216091

申请日：2002-08-09

申请人： Anthony J. Lochtefeld , Eugene A. Fitzgerald

发明人： Anthony J. Lochtefeld , Eugene A. Fitzgerald

IPC分类号： H01L21/337 , H01L29/10 , H01L29/165 , H01L29/80 , H01L23/48 , H01L23/52 , H01L29/40

CPC分类号： H01L29/66916 , H01L29/1054 , H01L29/165 , H01L29/802 , H01L2924/0002 , H01L2924/00

摘要： Semiconductor-based devices, and methods for making the devices, involve a first device that includes a buried channel layer, a dielectric layer, and a compositionally graded spacer layer. The spacer layer includes a first material and a second material, and is located between the buried channel layer and the dielectric layer. A second device includes a buried channel layer, a relaxed surface layer, and a spacer layer located between the buried channel layer and the relaxed surface layer. The spacer layer has a composition that is different from a composition of the relaxed layer. The spacer layer and the relaxed surface layer each have bandgap offsets relative to the buried channel layer to reduce a parasitic channel conduction. A substrate for fabrication of devices, and methods for making the substrate, involves a substrate that includes a first layer, such as a silicon wafer, a substantially uniform second layer, and a graded-composition third layer.

摘要翻译： 基于半导体的器件以及用于制造器件的方法包括第一器件，其包括掩埋沟道层，电介质层和组成分级的间隔层。间隔层包括第一材料和第二材料，并且位于掩埋沟道层和介电层之间。第二装置包括掩埋沟道层，松弛表面层和位于掩埋沟道层和松弛表面层之间的间隔层。间隔层具有与松弛层的组成不同的组成。间隔层和松弛表面层各自相对于掩埋沟道层具有带隙偏移，以减少寄生沟道传导。用于制造器件的衬底以及用于制造衬底的方法包括：衬底，其包括第一层，例如硅晶片，基本均匀的第二层和渐变组成的第三层。

14.

发明授权
Relaxed InxGa1-xAs layers integrated with Si 有权
标题翻译：与Si集成的轻松的In x Ga 1-x As层

公开(公告)号：US06594293B1

公开(公告)日：2003-07-15

申请号：US09779917

申请日：2001-02-08

申请人： Mayank Bulsara , Eugene A. Fitzgerald

发明人： Mayank Bulsara , Eugene A. Fitzgerald

IPC分类号： H01L3300

CPC分类号： C30B25/02 , C30B25/20 , C30B29/40 , C30B29/42 , H01L21/02381 , H01L21/0245 , H01L21/0251 , H01L21/02546

摘要： A method of processing semiconductor materials and a corresponding semiconductor structure, including providing a virtual substrate of a GaAs epitaxial film on a Si substrate, and epitaxailly growing a relaxed graded layer of InxGal-xAs at a temperature ranging upwards from about 600° C. with a subsequent process for planarization of the InGaAs alloy.

摘要翻译： 一种处理半导体材料的方法和相应的半导体结构，包括在Si衬底上提供GaAs外延膜的虚拟衬底，并且在约600℃的温度范围内将In x Ga 1-x As的弛豫梯度层上升生长，用于使InGaAs合金平坦化的后续工艺。

15.

发明授权
Low threading dislocation density relaxed mismatched epilayers without high temperature growth 有权

公开(公告)号：US06503773B2

公开(公告)日：2003-01-07

申请号：US09761497

申请日：2001-01-16

申请人： Eugene A. Fitzgerald

发明人： Eugene A. Fitzgerald

IPC分类号： H01L2100

CPC分类号： C30B25/02 , C30B29/40 , C30B29/42 , C30B29/52 , H01L21/02381 , H01L21/02392 , H01L21/02395 , H01L21/0245 , H01L21/02461 , H01L21/02463 , H01L21/02505 , H01L21/0251 , H01L21/02532 , H01L21/02543 , H01L21/02546 , H01L21/0262

摘要： A semiconductor structure and method of processing same including a substrate, a lattice-mismatched first layer deposited on the substrate and annealed at a temperature greater than 100° C. above the deposition temperature, and a second layer deposited on the first layer with a greater lattice mismatch to the substrate than the first semiconductor layer. In another embodiment there is provided a semiconductor graded composition layer structure on a semiconductor substrate and a method of processing same including a semiconductor substrate, a first semiconductor layer having a series of lattice-mismatched semiconductor layers deposited on the substrate and annealed at a temperature greater than 100° C. above the deposition temperature, a second semiconductor layer deposited on the first semiconductor layer with a greater lattice mismatch to the substrate than the first semiconductor layer, and annealed at a temperature greater than 100° C. above the deposition temperature of the second semiconductor layer.

16.

发明授权
Relaxed InxGa1−xAs buffers 失效
标题翻译：轻松的InxGa1-xAs缓冲液

公开(公告)号：US06495868B2

公开(公告)日：2002-12-17

申请号：US09804890

申请日：2001-03-13

申请人： Eugene A. Fitzgerald , Mayank T. Bulsara

发明人： Eugene A. Fitzgerald , Mayank T. Bulsara

IPC分类号： H01L3300

CPC分类号： H01L21/02543 , H01L21/02395 , H01L21/02463 , H01L21/0251 , H01L21/02546 , Y10S977/712

摘要： InxGa1−xAs structures with compositionally graded buffers grown with organometallic vapor phase epitaxy (OMPVE) on GaAs substrates. A semiconductor structure and a method of processing such a structure including providing a substrate of GaAs; and epitaxially growing a relaxed graded layer of InxGa1−xAs at a temperature ranging upwards from about 600° C.

摘要翻译： In x Ga 1-x As结构，其具有在GaAs衬底上用有机金属气相外延（OMPVE）生长的组成渐变缓冲液。一种半导体结构和处理这种结构的方法，包括提供GaAs的衬底; 并在约600℃的温度范围内外延生长In x Ga 1-x As的弛豫梯度层。

17.

发明授权
Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization 有权
标题翻译：使用梯度GeSi层和平面化控制Si中Ge中的穿透位错密度

公开(公告)号：US06291321B1

公开(公告)日：2001-09-18

申请号：US09265016

申请日：1999-03-09

申请人： Eugene A. Fitzgerald

发明人： Eugene A. Fitzgerald

IPC分类号： H01L2120

CPC分类号： H01L21/02505 , H01L21/02381 , H01L21/02433 , H01L21/0245 , H01L21/02502 , H01L21/0251 , H01L21/02532 , Y10S438/933

摘要： A semiconductor structure including a semiconductor substrate, at least one first crystalline epitaxial layer on the substrate, the first layer having a surface which is planarized, and at least one second crystalline epitaxial layer on the at least one first layer. In another embodiment of the invention there is provided a semiconductor structure including a silicon substrate, and a GeSi graded region grown on the silicon substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing. In yet another embodiment of the invention there is provided a semiconductor structure including a semiconductor substrate, a first layer having a graded region grown on the substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing, the first layer having a surface which is planarized, and a second layer provided on the first layer. In still another embodiment of the invention there is provided a method of fabricating a semiconductor structure including providing a semiconductor substrate, providing at least one first crystalline epitaxial layer on the substrate, and planarizing the surface of the first layer.

摘要翻译： 一种半导体结构，包括半导体衬底，在衬底上的至少一个第一晶体外延层，第一层具有被平坦化的表面，以及在至少一个第一层上的至少一个第二晶体外延层。在本发明的另一个实施例中，提供了包括硅衬底和在硅衬底上生长的GeSi分级区域的半导体结构，压缩应变被并入渐变区域以抵消在热处理期间结合的拉伸应变。在本发明的另一个实施例中，提供了一种半导体结构，其包括半导体衬底，具有在衬底上生长的渐变区域的第一层，压缩应变结合在渐变区域中以抵消在热处理期间结合的拉伸应变，所述第一层具有平坦化的表面，以及设置在所述第一层上的第二层。在本发明的另一个实施例中，提供了一种制造半导体结构的方法，包括提供半导体衬底，在衬底上提供至少一个第一晶体外延层，并平坦化第一层的表面。