公开(公告)号：US06660536B2

公开(公告)日：2003-12-09

申请号：US10080383

申请日：2002-02-21

Applicant: Kiyoshi Uchiyama ,  Carlos A. Paz de Araujo

Inventor： Kiyoshi Uchiyama ,  Carlos A. Paz de Araujo

IPC: H01L2100

CPC classification number: H01L27/10852 ,  H01L21/02197 ,  H01L21/3105 ,  H01L27/10808 ,  H01L28/55

Abstract: A ferroelectric thin film precursor material is annealed while in an electric field. The electric field is maintained as the material cools. A partially completed integrated circuit with a ferroelectric thin film precursor material may be placed between two electrodes in an annealing apparatus and voltage sufficient to polarize the ferroelectric thin film material in the direction of the electrical field is supplied to the electrodes during the anneal and as the film cools. Alternatively, probes are connected to the electrodes of a partially completed integrated circuit device and voltage sufficient to polarize the ferroelectric material is applied while annealing the material and as it cools. The anneal may be a furnace anneal or an RTP anneal.

Abstract translation: 铁电薄膜前体材料在电场中退火。 当材料冷却时，保持电场。 具有铁电薄膜前体材料的部分完成的集成电路可以在退火装置中放置在两个电极之间，并且在退火期间将足以使铁电薄膜材料沿电场方向偏振的电压供应到电极，并且作为 电影冷却 或者，探针连接到部分完成的集成电路器件的电极，并且在退火材料并且在其冷却时施加足以极化铁电材料的电压。 退火可以是炉退火或RTP退火。

公开(公告)号：US06605477B2

公开(公告)日：2003-08-12

申请号：US10262003

申请日：2002-09-30

Applicant: Kiyoshi Uchiyama

Inventor： Kiyoshi Uchiyama

IPC: H01L2100

CPC classification number: H01L21/02197 ,  H01L21/02356 ,  H01L21/31691 ,  H01L28/56

Abstract: An integrated circuit memory device includes a thin film layered superlattice material layer and an electrode. An interface buffer layer is formed between said thin film layered superlattice material layer and said electrode. The interface buffer layer is selected from the group consisting of: 1) simple oxides, not including bismuth, of an A-site or a B-site metal; and 2) second layered superlattice materials different from the first layered superlattice material and containing at least one A-site or B-site metal that is the same as an A-site or B-site metal in the first layered superlattice material. The oxide not including bismuth can be a complex oxide including a plurality of metals or a simple oxide including only one metal. Most preferably, the interface buffer layer is selected from the group consisting of strontium tantalate, bismuth tantalate, strontium niobium tantalate, strontium bismuth tantalate niobate, titanium oxide, and tantalum pentoxide, other simple oxides of A-site and B-site metals, and other simple oxides of one or more A-site or B-site metals.

公开(公告)号：US5222074A

公开(公告)日：1993-06-22

申请号：US709280

申请日：1991-06-03

Applicant: Kiyoshi Uchiyama ,  Tomoko Suzuki ,  Tatsuo Yokotsuka ,  Akira Takamori ,  Masato Nakajima

Inventor： Kiyoshi Uchiyama ,  Tomoko Suzuki ,  Tatsuo Yokotsuka ,  Akira Takamori ,  Masato Nakajima

IPC: C30B23/08 ,  C23C14/24 ,  C23C16/452 ,  C30B23/06 ,  H01L21/203

CPC classification number: C30B23/066 ,  C23C14/24 ,  C23C16/452

Abstract: A thermal decomposition cell for producing a molecular beam from a material gas, includes: a crucible maintained at a given temperature necessary for thermal decomposition of the material gas which is effused in the crucible in a given direction; and a thermal decomposition baffle provided in the crucible and heated to a given temperature necessary for thermal decomposition of the material gas for producing the molecular beam by thermal-decomposing of the material gas such that the material gas is baffled in substantially all directions, the thermal decomposition baffle being made of a given metal to cause the thermal decomposition of the material gas. The thermal decomposition baffle may comprise a fiber or a cloth made of the metal loaded in the crucible. The thermal decomposition baffle may comprise a plurality of different sized rooms made of the given metal, each of said rooms having fine holes to allow the material gas to pass therethrough, and successively arranged in such a manner that said material gas moves from one room toward the other adjacent thereto.

公开(公告)号：US06876030B2

公开(公告)日：2005-04-05

申请号：US09956556

申请日：2001-09-20

Applicant: Kiyoshi Uchiyama ,  Yasuhiro Shimada ,  Koji Arita ,  Tatsuo Otsuki

Inventor： Kiyoshi Uchiyama ,  Yasuhiro Shimada ,  Koji Arita ,  Tatsuo Otsuki

IPC: B65G1/137 ,  G11C11/22 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/51 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76

CPC classification number: H01L29/516 ,  H01L29/78391 ,  H01L29/7881

Abstract: A semiconductor memory device includes a field-effect transistor with a gate electrode that has been formed over a semiconductor substrate with a ferroelectric layer interposed between the electrode and the substrate. The device includes a first insulating layer, which is insulated against a leakage current more fully than the ferroelectric layer, between the ferroelectric layer and the gate electrode.

Abstract translation: 半导体存储器件包括具有栅极电极的场效应晶体管，该栅极电极已经形成在半导体衬底上，其中介于电极和衬底之间的铁电层。 该器件包括第一绝缘层，其在铁电层和栅电极之间绝对抵抗比铁电层更全面的泄漏电流。

公开(公告)号：US06562678B1

公开(公告)日：2003-05-13

申请号：US09521094

申请日：2000-03-07

Applicant: Kiyoshi Uchiyama ,  Narayan Solayappan ,  Carlos A. Paz de Araujo

Inventor： Kiyoshi Uchiyama ,  Narayan Solayappan ,  Carlos A. Paz de Araujo

IPC: H01L218242

CPC classification number: C23C16/45561 ,  C23C16/0272 ,  C23C16/40 ,  C23C16/44 ,  Y10S438/935 ,  Y10S438/938

Abstract: A first reactant gas is flowed into a CVD reaction chamber containing a heated integrated circuit substrate. The first reactant gas contains a first precursor compound or a plurality of first precursor compounds, and the first precursor compound or compounds decompose in the CVD reaction chamber to deposit a coating containing metal atoms on the heated integrated circuit substrate. The coating is treated by RTP. Thereafter, a second reactant gas is flowed into a CVD reaction chamber containing the heated substrate. The second reactant gas contains a second precursor compound or a plurality of second precursor compounds, which decompose in the CVD reaction chamber to deposit more metal atoms on the substrate. Heat for reaction and crystallization of the deposited metal atoms to form a thin film of layered superlattice material is provided by heating the substrate during CVD deposition, as well as by selected rapid thermal processing (“RTP”) and furnace annealing steps.

公开(公告)号：US06489645B1

公开(公告)日：2002-12-03

申请号：US09898927

申请日：2001-07-03

Applicant: Kiyoshi Uchiyama

Inventor： Kiyoshi Uchiyama

IPC: H01L2976

CPC classification number: H01L21/02197 ,  H01L21/02356 ,  H01L21/31691 ,  H01L28/56

Abstract: An integrated circuit memory device includes a thin film layered superlattice material layer and an electrode. An interface buffer layer is formed between said thin film layered superlattice material layer and said electrode. The interface buffer layer is selected from the group consisting of: 1) simple oxides, not including bismuth, of an A-site or a B-site metal; and 2) second layered superlattice materials different from the first layered superlattice material and containing at least one A-site or B-site metal that is the same as an A-site or B-site metal in the first layered superlattice material. The oxide not including bismuth can be a complex oxide including a plurality of metals or a simple oxide including only one metal. Most preferably, the interface buffer layer is selected from the group consisting of strontium tantalate, bismuth tantalate, strontium niobium tantalate, strontium bismuth tantalate niobate, titanium oxide, and tantalum pentoxide, other simple oxides of A-site and B-site metals, and other simple oxides of one or more A-site or B-site metals.

Abstract translation: 集成电路存储器件包括薄膜层状超晶格材料层和电极。 在所述薄膜层状超晶格材料层和所述电极之间形成界面缓冲层。 界面缓冲层选自：1）A位或B位金属的简单氧化物，不包括铋; 和2）与第一层状超晶格材料不同的第二层超晶格材料，并且在第一层状超晶格材料中含有与A位或B位金属相同的至少一个A位或B位金属。 不包括铋的氧化物可以是包括多种金属的复合氧化物或仅包括一种金属的简单氧化物。 最优选的界面缓冲层选自钽酸锶，钽酸铋，钽酸锶铌酸铌，铌酸铋铋，二氧化钛，五氧化二钽，A位和B位金属的其它简单氧化物，以及 一个或多个A位或B位金属的其它简单氧化物。

公开(公告)号：US06396095B1

公开(公告)日：2002-05-28

申请号：US09869522

申请日：2001-06-29

Applicant: Yasuhiro Shimada ,  Koji Arita ,  Kiyoshi Uchiyama

Inventor： Yasuhiro Shimada ,  Koji Arita ,  Kiyoshi Uchiyama

IPC: H01L2976

CPC classification number: G11C11/22 ,  H01L21/28291 ,  H01L29/42324 ,  H01L29/516 ,  H01L29/78391

Abstract: Source/drain regions for a field effect transistor are defined in a semiconductor substrate with a channel region interposed therebetween. A first gate electrode is formed over the semiconductor substrate with an insulating film sandwiched therebetween and has a gate length shorter than the length of the channel region. A ferroelectric film is formed to cover the first gate electrode and to have both side portions thereof make contact with the insulating film. A second gate electrode is formed to cover the ferroelectric film.

Abstract translation: 用于场效应晶体管的源极/漏极区限定在其间插入沟道区的半导体衬底中。 第一栅电极形成在半导体衬底之上，绝缘膜夹在其间，栅极长度短于沟道区的长度。 形成铁电膜以覆盖第一栅电极并且使其两侧部分与绝缘膜接触。 形成第二栅电极以覆盖铁电体膜。

公开(公告)号：US06351004B1

公开(公告)日：2002-02-26

申请号：US09688494

申请日：2000-10-16

Applicant: Yasuhiro Shimada ,  Shinichiro Hayashi ,  Kiyoshi Uchiyama ,  Keisuke Tanaka

Inventor： Yasuhiro Shimada ,  Shinichiro Hayashi ,  Kiyoshi Uchiyama ,  Keisuke Tanaka

IPC: H01L2978

CPC classification number: H01L29/6684 ,  H01L21/28291 ,  H01L29/772 ,  H01L29/78391

Abstract: A tunneling transistor is provided as an effective means for miniaturization of a semiconductor integrated circuit having nonvolatile memory. An insulating layer is disposed on a silicon substrate. A source and a drain are disposed on the insulating layer, with an insulator of a few nanometers in thickness that provides a tunnel barrier being interposed between the source and the drain. A ferroelectric layer that exhibits spontaneous polarization is disposed directly above a region of the source that is adjacent to the insulator. With this construction, when the ferroelectric layer is polarized in a predetermined direction, at least a portion of the region of the source adjacent to the insulator forms a depletion region, with it being possible to vary the amount of current tunneling through the insulator depending on whether the ferroelectric layer is polarized or not.

Abstract translation: 提供隧道晶体管作为具有非易失性存储器的半导体集成电路的小型化的有效手段。 绝缘层设置在硅衬底上。 源极和漏极设置在绝缘层上，具有几纳米厚度的绝缘体，其提供了在源极和漏极之间插入的隧道势垒。 显示自发极化的铁电层直接设置在与绝缘体相邻的源极的正上方。 利用这种结构，当铁电层在预定方向上极化时，与绝缘体相邻的源极的区域的至少一部分形成耗尽区，根据该结构，可以改变通过绝缘体的电流隧穿量 铁电层是否极化。

公开(公告)号：US5194400A

公开(公告)日：1993-03-16

申请号：US800376

申请日：1991-11-29

Applicant: Akira Takamori ,  Ken Idota ,  Kiyoshi Uchiyama ,  Masato Nakajima

Inventor： Akira Takamori ,  Ken Idota ,  Kiyoshi Uchiyama ,  Masato Nakajima

IPC: H01S5/00 ,  H01L21/20

CPC classification number: H01L21/02631 ,  H01L21/02395 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02543 ,  Y10S148/095

Abstract: A method for fabricating an AlGaInP-based visible light laser device by molecular beam epitaxy is described. In this method, a upper clad layer of (Al.sub.x Ga.sub.1-x).sub.y In.sub.1-y P wherein x and y are, respectively, in the ranges of from 0.5 to 1 and from 0.47 to 0.53 is covered with a protective layer serving also as an etching prevenive layer so that a grooved-type structure using the (Al.sub.x Ga.sub.1-x).sub.y In.sub.1-y P clad layer can be fabricated without involving degradation of the clad layer by contamination with oxygen, nitrogen and the like.

Abstract translation: 描述了通过分子束外延制造基于AlGaInP的可见光激光器件的方法。 在这种方法中，其中x和y分别在0.5至1和0.47至0.53的范围内的（Al x Ga 1-x）y In 1-y P的上包层覆盖有也用作蚀刻预处理的保护层 使得可以制造使用（Al x Ga 1-x）y In 1-y P包覆层的沟槽型结构，而不会由于氧，氮等的污染而导致包覆层劣化。