公开(公告)号：US07998830B2

公开(公告)日：2011-08-16

申请号：US12961167

申请日：2010-12-06

申请人： Chung Long Cheng ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang ,  Mong-Song Liang

发明人： Chung Long Cheng ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang ,  Mong-Song Liang

IPC分类号： H01L21/76

CPC分类号： H01L29/66477 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/0629 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/7848

摘要： A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.

摘要翻译： 具有具有高k栅极电介质的核心器件和具有二氧化硅或其它非高k栅极电介质的I / O器件的半导体器件及其制造方法。 核心阱和I / O阱在半导体衬底中产生并被隔离结构隔开。 I / O器件形成在I / O阱上，并具有二氧化硅或低k栅极电介质。 可以在与芯井相邻的隔离结构上形成电阻器。 在核心阱上形成诸如晶体管的核心阱器件，并且具有高k栅极电介质。 在一些实施例中，产生p型I / O阱和n型I / O阱。 在优选实施例中，在形成核心器件之前形成I / O器件或器件，并用牺牲层进行保护，直到制造核心器件。

公开(公告)号：US07772701B2

公开(公告)日：2010-08-10

申请号：US11422769

申请日：2006-06-07

申请人： Chih-Hsiang Yao ,  Tai-Chun Huang ,  Mong-Song Liang

发明人： Chih-Hsiang Yao ,  Tai-Chun Huang ,  Mong-Song Liang

IPC分类号： H01L23/48 ,  H01L29/40

CPC分类号： H01L23/522 ,  H01L23/481 ,  H01L23/53228 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2924/0002 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2924/00

摘要： An improved integrated circuit structure and method of making the same is provided. The integrated circuit structure comprises a substrate, the substrate having a top surface and a bottom surface. The top surface has a circuit device formed thereon. The structure includes a plurality of metallization layers, a bonding structure formed over the bottom surface and a conductive interconnect structure formed through said substrate.

摘要翻译： 提供了一种改进的集成电路结构及其制造方法。 集成电路结构包括基板，该基板具有顶表面和底表面。 顶表面上形成有电路装置。 该结构包括多个金属化层，形成在底表面上的接合结构和通过所述衬底形成的导电互连结构。

公开(公告)号：US20100001332A1

公开(公告)日：2010-01-07

申请号：US12256132

申请日：2008-10-22

申请人： Harry Chuang ,  Tzung-Chi Lee ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Mong-Song Liang

发明人： Harry Chuang ,  Tzung-Chi Lee ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Mong-Song Liang

IPC分类号： H01L29/92 ,  H01L21/34

CPC分类号： H01L27/0629 ,  H01L27/11 ,  H01L29/94

摘要： A semiconductor device is provided which includes a semiconductor substrate having a first region and a second region, transistors having metal gates formed in the first region, and at least one capacitor formed in the second region. The capacitor includes a top electrode having at least one stopping structure formed in the top electrode, the at least one stopping structure being of a different material from the top electrode, a bottom electrode, and a dielectric layer interposed between the top electrode and the bottom electrode.

摘要翻译： 提供一种半导体器件，其包括具有第一区域和第二区域的半导体衬底，在第一区域中形成有金属栅极的晶体管，以及形成在第二区域中的至少一个电容器。 所述电容器包括顶电极，所述顶电极具有形成在所述顶电极中的至少一个止动结构，所述至少一个止动结构与所述顶电极，底电极和介于所述顶电极和所述底电极之间的电介质层具有不同的材料 电极。

公开(公告)号：US20090224337A1

公开(公告)日：2009-09-10

申请号：US12467847

申请日：2009-05-18

申请人： Ming-Hua Yu ,  Mong-Song Liang ,  Tze-Liang Lee ,  Jr-Hung Li

发明人： Ming-Hua Yu ,  Mong-Song Liang ,  Tze-Liang Lee ,  Jr-Hung Li

IPC分类号： H01L29/78

CPC分类号： H01L29/7848 ,  H01L29/045 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7836 ,  Y10S438/938

摘要： A semiconductor structure includes a semiconductor substrate having a first lattice constant; a gate dielectric on the semiconductor substrate; a gate electrode on the semiconductor substrate; and a stressor having at least a portion in the semiconductor substrate and adjacent the gate electrode. The stressor has a tilted sidewall on a side adjacent the gate electrode. The stressor includes a first stressor layer having a second lattice constant substantially different from the first lattice constant; and a second stressor layer on the first stressor layer, wherein the second stressor has a third lattice constant substantially different from the first and the second lattice constants.

摘要翻译： 半导体结构包括具有第一晶格常数的半导体衬底; 半导体衬底上的栅极电介质; 半导体衬底上的栅电极; 以及在半导体衬底中具有至少一部分并且与栅电极相邻的应力源。 应力源在与栅电极相邻的一侧具有倾斜的侧壁。 应激源包括具有与第一晶格常数基本不同的第二晶格常数的第一应力层; 以及第一应力层上的第二应力层，其中第二应力源具有与第一和第二晶格常数基本上不同的第三晶格常数。

公开(公告)号：US20080093682A1

公开(公告)日：2008-04-24

申请号：US11583491

申请日：2006-10-18

申请人： Liang-Gi Yao ,  Jin Ying ,  Hun-Jan Tao ,  Shih-Chang Chen ,  Mong-Song Liang

发明人： Liang-Gi Yao ,  Jin Ying ,  Hun-Jan Tao ,  Shih-Chang Chen ,  Mong-Song Liang

IPC分类号： H01L29/76

CPC分类号： H01L21/823443 ,  H01L21/28097 ,  H01L21/823835 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7833

摘要： Semiconductor structures having a silicided gate electrode and methods of manufacture are provided. A device comprises a first silicided structure formed in a first active region and a second silicided structure formed in a second active region. The two silicided structures have different metal concentrations. A method of forming a silicided device comprises forming a polysilicon structure on the first and second device fabrication regions. Embodiments include replacing a first portion of the polysilicon structure on the first device fabrication region with a metal and replacing a second portion of the polysilicon structure on the second device fabrication region with the metal. Preferably, the second portion is different than the first portion. Embodiments further include reacting the polysilicon structures on the first and second device fabrication regions with the metal to form a silicide.

摘要翻译： 提供了具有硅化物栅电极和制造方法的半导体结构。 一种器件包括形成在第一有源区中的第一硅化结构和形成在第二有源区中的第二硅化结构。 两个硅化物结构具有不同的金属浓度。 形成硅化器件的方法包括在第一和第二器件制造区域上形成多晶硅结构。 实施例包括用金属替代第一器件制造区上的多晶硅结构的第一部分，并用金属代替第二器件制造区上的多晶硅结构的第二部分。 优选地，第二部分不同于第一部分。 实施例还包括使第一和第二器件制造区上的多晶硅结构与金属反应以形成硅化物。

公开(公告)号：US20080003734A1

公开(公告)日：2008-01-03

申请号：US11520377

申请日：2006-09-13

申请人： Harry Chuang ,  Mong-Song Liang ,  Kong-Beng Thei ,  Jung-Hui Kao ,  Chung Long Cheng ,  Sheng-Chen Chung ,  Wen-Huei Guo

发明人： Harry Chuang ,  Mong-Song Liang ,  Kong-Beng Thei ,  Jung-Hui Kao ,  Chung Long Cheng ,  Sheng-Chen Chung ,  Wen-Huei Guo

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/7843

摘要： A method of forming a semiconductor structure includes providing a semiconductor substrate comprising a first region and a second region, forming a first PMOS device in the first region wherein a first gate electrode of the first PMOS device has a first p-type impurity concentration, forming a stress memorization layer over the first PMOS device, reducing the stress memorization layer in the first region, performing an annealing after the step of reducing the stress memorization layer in the first region, and removing the stress memorization layer. The same stress memorization layer is not reduced in a region having an NMOS device. The same stress memorization layer may not be reduced in a region including a second PMOS device.

摘要翻译： 一种形成半导体结构的方法包括提供包括第一区域和第二区域的半导体衬底，在第一区域中形成第一PMOS器件，其中第一PMOS器件的第一栅电极具有第一p型杂质浓度，形成 在第一PMOS器件上方的应力记忆层，减小第一区域中的应力存储层，在减少第一区域中的应力存储层的步骤之后进行退火，以及去除应力存储层。 在具有NMOS器件的区域中，相同的应力记忆层没有减小。 在包括第二PMOS器件的区域中，相同的应力记忆层可能不会减小。

公开(公告)号：US07247915B2

公开(公告)日：2007-07-24

申请号：US11375778

申请日：2006-03-15

申请人： Chih-Wei Chang ,  Mei-Yun Wang ,  Shau-Lin Shue ,  Mong-Song Liang

发明人： Chih-Wei Chang ,  Mei-Yun Wang ,  Shau-Lin Shue ,  Mong-Song Liang

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L21/28518 ,  H01L29/4941 ,  H01L29/665 ,  H01L29/7833

摘要： A silicide method for integrated circuit and semiconductor device fabrication wherein a layer of nickel is formed over at least one silicon region of a substrate and a layer of cobalt is formed over the nickel layer. The cobalt/nickel bi-layer is then annealed to transform the bi-layer to a bi-silicide film having a cobalt-rich silicide portion and a nickel-rich silicide portion.

摘要翻译： 一种用于集成电路和半导体器件制造的硅化物方法，其中在镍层上形成在衬底的至少一个硅区域上形成镍层并且形成钴层。 然后退火钴/镍双层以将双层转变为具有富钴硅化物部分和富镍硅化物部分的双硅化物膜。

公开(公告)号：US20070152306A1

公开(公告)日：2007-07-05

申请号：US11324334

申请日：2006-01-04

申请人： Chien-Hsueh Shih ,  Shau-Lin Shue ,  Mong-Song Liang ,  Chao-Hsien Peng

发明人： Chien-Hsueh Shih ,  Shau-Lin Shue ,  Mong-Song Liang ,  Chao-Hsien Peng

IPC分类号： H01L23/58 ,  H01L21/4763

CPC分类号： H01L21/2885 ,  C23C18/1889 ,  C23C18/1893 ,  C25D5/54 ,  C25D13/04 ,  H01L21/76843 ,  H01L21/76873 ,  H01L21/76877

摘要： A semiconductor device and fabrication method thereof. The semiconductor device comprises a substrate, an electroactive organic layer with conformal step coverage and uniform thickness, and a metal layer. The substrate is a conductive substrate or a nonconductive substrate with a conductive layer formed thereon. The electroactive organic layer and the metal layer are formed sequentially on the conductive substrate or the conductive layer, wherein the electroactive organic layer comprises metal atoms and serves as a seed layer, resulting in the metal layer formed in-situ.

摘要翻译： 半导体器件及其制造方法。 半导体器件包括基底，具有适形阶梯覆盖和均匀厚度的电活性有机层和金属层。 衬底是其上形成有导电层的导电衬底或非导电衬底。 所述电活性有机层和所述金属层依次形成在所述导电性基板或所述导电层上，其中所述电活性有机层包含金属原子并且用作种子层，导致所述金属层原位形成。

公开(公告)号：US07202142B2

公开(公告)日：2007-04-10

申请号：US10838721

申请日：2004-05-03

申请人： Kuen-Chyr Lee ,  Liang-Gi Yao ,  Shih-Chang Chen ,  Mong-Song Liang

发明人： Kuen-Chyr Lee ,  Liang-Gi Yao ,  Shih-Chang Chen ,  Mong-Song Liang

IPC分类号： H01L21/20

CPC分类号： H01L29/1054 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/665 ,  H01L29/78

摘要： A silicon strained channel MOSFET device and method for forming the same the method providing improved wafer throughput and low defect density including the steps of providing a silicon substrate; epitaxially growing a first silicon layer using at least one deposition precursor selected from the group consisting of disilane, trisilane, dichlorosilane, and silane; epitaxially growing a step-grade SiGe buffer layer over and contacting the first silicon layer using at least one deposition precursor selected from the group consisting of disilane and trisilane; epitaxially growing a SiGe capping layer over and contacting the step-grade SiGe buffer layer using at least one deposition precursor selected from the group consisting of disilane and trisilane; and, epitaxially growing a second silicon layer using at least one deposition precursor selected from the group consisting of disilane, trisilane, dichlorosilane, and silane.

摘要翻译： 一种硅应变通道MOSFET器件及其形成方法，该方法提供提供晶片生产能力和低缺陷密度的方法，包括提供硅衬底的步骤; 使用选自乙硅烷，丙硅烷，二氯硅烷和硅烷的至少一种沉积前体外延生长第一硅层; 使用选自乙硅烷和丙硅烷的至少一种沉积前体外延生长阶梯级SiGe缓冲层并使第一硅层接触; 使用至少一种选自乙硅烷和丙硅烷的沉积前体外延生长SiGe覆盖层并使其与阶级SiGe缓冲层接触; 并且使用至少一种选自乙硅烷，丙硅烷，二氯硅烷和硅烷的沉积前体外延生长第二硅层。

公开(公告)号：US20070026668A1

公开(公告)日：2007-02-01

申请号：US11457888

申请日：2006-07-17

申请人： Hun-Jan Tao ,  Ryan Chen ,  Mong-Song Liang

发明人： Hun-Jan Tao ,  Ryan Chen ,  Mong-Song Liang

IPC分类号： H01L21/465

CPC分类号： H01L21/31116 ,  H01L21/76802 ,  H01L21/76807

摘要： A method of removing a silicon nitride or a nitride-based bottom etch stop layer in a copper damascene structure by etching the bottom etch stop layer is disclosed, with the method using a high density, high radical concentration plasma containing fluorine and oxygen to minimize back sputtering of copper underlying the bottom etch stop layer and surface roughening of the low-k interlayer dielectric caused by the plasma.

摘要翻译： 公开了一种通过蚀刻底部蚀刻停止层去除铜镶嵌结构中的氮化硅或氮化物基底部蚀刻停止层的方法，该方法使用含有氟和氧的高密度，高自由基浓度等离子体来最小化背面 底层蚀刻停止层下面的铜的溅射以及由等离子体引起的低k层间电介质的表面粗糙化。