公开(公告)号：US08108181B2

公开(公告)日：2012-01-31

申请号：US12950762

申请日：2010-11-19

申请人： Neil Y. Kim ,  Pieter Vorenkamp

发明人： Neil Y. Kim ,  Pieter Vorenkamp

IPC分类号： G06F19/00

CPC分类号： G05F1/66 ,  G01K13/00 ,  G01R31/28 ,  G06F11/3409 ,  G06F17/00 ,  H02J13/0003 ,  Y02B90/228 ,  Y02D10/34 ,  Y04S20/18

摘要： A system and method for controlling performance and/or power based on monitored performance characteristics. Various aspects of the present invention may comprise an integrated circuit comprising a first circuit module that receives electrical power. A second circuit module may monitor one or more performance characteristics of the first circuit module and/or the integrated circuit. A third circuit module may, for example, determine power control information based at least in part on the monitored performance characteristic(s). The power control information may be communicated to power supply circuitry to control various characteristics of the electrical power. Various aspects of the present invention may also comprise an integrated circuit comprising a first module that monitors at least one performance characteristic of a first electrical device. The integrated circuit may also comprise modules that determine power control information based on the monitored performance characteristic(s) and communicate such power control information to power supply circuitry.

摘要翻译： 基于监测的性能特征来控制性能和/或功率的系统和方法。 本发明的各个方面可以包括集成电路，其包括接收电力的第一电路模块。 第二电路模块可以监视第一电路模块和/或集成电路的一个或多个性能特性。 第三电路模块可以例如至少部分地基于所监视的性能特征来确定功率控制信息。 功率控制信息可以传送到电源电路以控制电力的各种特性。 本发明的各个方面还可以包括集成电路，其包括监测第一电气设备的至少一个性能特征的第一模块。 集成电路还可以包括基于所监视的性能特征来确定功率控制信息并将这种功率控制信息传送到电源电路的模块。

公开(公告)号：US20110304394A1

公开(公告)日：2011-12-15

申请号：US12961151

申请日：2010-12-06

申请人： Klaas Bult ,  Rudy van de Plassche ,  Pieter Vorenkamp ,  Arnoldus Venes

发明人： Klaas Bult ,  Rudy van de Plassche ,  Pieter Vorenkamp ,  Arnoldus Venes

IPC分类号： H03F3/45

CPC分类号： H03G3/30 ,  H03F1/34 ,  H03F3/195 ,  H03F3/24 ,  H03F3/45188 ,  H03F3/45192 ,  H03F2200/294 ,  H03F2200/331 ,  H03F2200/372 ,  H03F2200/513 ,  H03F2203/45644 ,  H03G1/0029 ,  H04B2001/0433

摘要： An integrated communications system. Comprising a substrate having a receiver disposed on the substrate for converting a received signal to an IF signal. Coupled to a VGA for low voltage applications and coupled to the receiver for processing the IF signal. The VGA includes a bank pair having a first bank of differential pairs of transistors and a second bank of differential pairs of transistors. The bank pair is cross-coupled in parallel, the IF signal is applied to the bank pair decoupled from a control signal used to control transconductance output gain of the bank pair over a range of input voltages. A digital IF demodulator is disposed on the substrate and coupled to the VGA for low voltage applications, for converting the IF signal to a demodulated baseband signal. And a transmitter is disposed on the substrate operating in cooperation with the receiver to establish a two way communications path.

摘要翻译： 综合通信系统。 包括具有设置在基板上的接收器的基板，用于将接收信号转换成IF信号。 耦合到VGA用于低电压应用并耦合到接收机处理IF信号。 VGA包括具有第一组差分晶体管组和第二组差分晶体管组的存储体对。 银行对并行交叉耦合，IF信号被施加到从用于在一定范围的输入电压上控制存储体对的跨导输出增益的控制信号去耦的存储体对。 数字IF解调器设置在衬底上并耦合到用于低电压应用的VGA，用于将IF信号转换成解调的基带信号。 并且发射机设置在与接收器协作操作的基板上以建立双向通信路径。

公开(公告)号：US08000083B2

公开(公告)日：2011-08-16

申请号：US12511398

申请日：2009-07-29

申请人： Victor Chiu-Kit Fong ,  Eric Bruce Blecker ,  Tom W. Kwan ,  Ning Li ,  Sumant Ranganathan ,  Chao Tang ,  Pieter Vorenkamp

发明人： Victor Chiu-Kit Fong ,  Eric Bruce Blecker ,  Tom W. Kwan ,  Ning Li ,  Sumant Ranganathan ,  Chao Tang ,  Pieter Vorenkamp

IPC分类号： H01G4/06

CPC分类号： H01L23/5223 ,  H01L23/5225 ,  H01L27/0207 ,  H01L27/0805 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to form the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance.

摘要翻译： 本发明提供了几种可扩展的集成电路高密度电容器及其布局技术。 电容器例如通过改变金属层的数量和/或用于形成电容器的金属层的面积来缩放。 电容器使用不同的金属化图案来形成金属层，以及不同的通孔图案以耦合相邻的金属层。 在实施例中，可选屏蔽包括作为电容器的最顶层和/或最底层，和/或作为侧屏蔽，以减少不必要的寄生电容。

公开(公告)号：US07925906B2

公开(公告)日：2011-04-12

申请号：US11166632

申请日：2005-06-24

申请人： Sumant Ranganathan ,  Pieter Vorenkamp ,  Neil Y. Kim ,  Chun-ying Chen

发明人： Sumant Ranganathan ,  Pieter Vorenkamp ,  Neil Y. Kim ,  Chun-ying Chen

IPC分类号： G06F1/26 ,  G06F1/32

CPC分类号： G06F1/26 ,  Y10T307/352

摘要： A system and method for implementing a multi-voltage multi-battery power management integrated circuit. Various aspects of the present invention provide a power management integrated circuit. The power management IC may comprise a first regulator module that receives a first battery power signal from a first battery characterized by a first battery voltage and outputs a first regulated power signal, based at least in part on the first battery power signal. The power management IC may also comprise a second regulator module that receives a second battery power signal from a second battery characterized by a second battery voltage and outputs a second regulated power signal, based at least in part on the second battery power signal. The second battery voltage may, for example, be substantially different than the first battery voltage. The power first and second regulated power signals may, for example, correspond to substantially different power supply voltages.

摘要翻译： 一种实现多电压多电池电源管理集成电路的系统和方法。 本发明的各个方面提供一种功率管理集成电路。 电源管理IC可以包括第一调节器模块，该第一调节器模块至少部分地基于第一电池电力信号从第一电池接收特征在于第一电池电压并输出第一调节功率信号的第一电池电力信号。 电源管理IC还可以包括第二调节器模块，该第二调节器模块至少部分地基于第二电池电力信号从第二电池接收特征为第二电池电压并输出第二调节功率信号的第二电池电力信号。 例如，第二电池电压可能与第一电池电压基本上不同。 功率第一和第二调节功率信号可以例如对应于基本上不同的电源电压。

公开(公告)号：US07782094B2

公开(公告)日：2010-08-24

申请号：US11654031

申请日：2007-01-17

申请人： Pieter Vorenkamp

发明人： Pieter Vorenkamp

IPC分类号： H03K5/153

CPC分类号： G06F1/26 ,  G06F1/266 ,  H04B3/44 ,  H04L12/10 ,  H04L12/40045 ,  H04L25/02 ,  Y10S370/91 ,  Y10T307/724

摘要： Power over Ethernet (PoE) communication systems provide power and data communications over the same communications link, where a power source device (PSE) provides DC power (for example, 48 volts DC) to a powered device (PD). The DC power is transmitted simultaneously over the same communications medium with the high speed data from one node to the other node. The PSE typically includes a controller that controls the DC power provided to the PD at the second node of the communications link. The PSE controller measures the voltage, current, and temperature of the outgoing and incoming DC supply lines to characterize the power requirements of the PD. The PSE controller includes a resistorless switch to measure the current. The resistorless switch includes a sense transistor and a current mirror to allowing the PSE controller to calculate the current based upon a replica current.

摘要翻译： 以太网供电（PoE）通信系统通过相同的通信链路提供电力和数据通信，其中电源设备（PSE）向被动设备（PD）提供DC电力（例如，48伏DC）。 DC功率通过相同的通信介质同时传输，高速数据从一个节点到另一个节点。 PSE通常包括控制器，其控制在通信链路的第二节点处提供给PD的DC电力。 PSE控制器测量输出和输入直流电源线路的电压，电流和温度，以表征PD的功率需求。 PSE控制器包括一个无电阻开关来测量电流。 无电阻开关包括检测晶体管和电流镜，以允许PSE控制器基于复制电流来计算电流。

公开(公告)号：US20090251326A1

公开(公告)日：2009-10-08

申请号：US12484430

申请日：2009-06-15

申请人： Neil Y. Kim ,  Pieter Vorenkamp ,  Sumant Ranganathan ,  Chun-Ying Chen

发明人： Neil Y. Kim ,  Pieter Vorenkamp ,  Sumant Ranganathan ,  Chun-Ying Chen

IPC分类号： G08B21/00

CPC分类号： H02J7/0047 ,  H04M1/72519 ,  H04W52/0258 ,  Y02D70/00

摘要： A system and method for providing a low power warning in a portable communication device based on predicted device utilization. Various aspects of the present invention may comprise monitoring power utilization for a portable communication device. A power utilization profile may be determined based, at least in part, on the results of the power utilization monitoring. Power availability for the portable communication device may be determined. Future power need for the portable communication device may be predicted based, at least in part, on the determined power utilization profile. The predicted future power need and the determined power availability may be analyzed to determine whether to generate a warning indicating a potential future power shortage. If it is determined that a potential future power shortage warning should be generated, such a warning may be generated. Such a warning may, for example, be generated in accordance with user specifications.

摘要翻译： 一种用于基于预测的设备利用率在便携式通信设备中提供低功率警告的系统和方法。 本发明的各个方面可以包括监视便携式通信设备的功率利用。 可以至少部分地基于功率利用率监测的结果来确定功率利用率曲线。 可以确定便携式通信设备的功率可用性。 可以至少部分地基于确定的功率利用率曲线来预测便携式通信设备的未来功率需求。 可以分析预测的未来功率需求和确定的功率可用性，以确定是否产生指示潜在的未来电力短缺的警告。 如果确定应该产生潜在的未来电力短缺警告，则可能产生这种警告。 这样的警告可以例如根据用户规格生成。

公开(公告)号：US07586987B2

公开(公告)日：2009-09-08

申请号：US10680490

申请日：2003-10-08

申请人： Pieter Vorenkamp ,  Aaron Buchwald

发明人： Pieter Vorenkamp ,  Aaron Buchwald

IPC分类号： H04B3/00 ,  H04L25/03

CPC分类号： H04L25/03878 ,  H04B3/144

摘要： A high speed data link includes transmitter equalization and (passive) receiver equalization to compensate for frequency distortion of the data link. In one embodiment, the transmitter equalization is performed with a de-emphasis circuit. The transmitter de-emphasis circuit pre-distorts an input signal to compensate for at least some of the frequency distortion in the data caused by the transmission line. The (passive) receive equalization circuit further compensates for the frequency distortion at the output of the transmission line to flatten the amplitude response of the output signal, and thereby reduce inter-symbol interference, improve media reach and improve the bit error rate (BER).

摘要翻译： 高速数据链路包括发射机均衡和（无源）接收机均衡以补偿数据链路的频率失真。 在一个实施例中，用去加重电路来执行发射机均衡。 发射机去加重电路预失真输入信号，以补偿由传输线引起的数据中的至少一些频率失真。 （无源）接收均衡电路进一步补偿传输线输出端的频率失真，使输出信号的振幅响应平坦化，从而减少符号间干扰，提高媒体距离，提高误码率（BER） 。

公开(公告)号：US20080284919A1

公开(公告)日：2008-11-20

申请号：US12219925

申请日：2008-07-30

申请人： Pieter Vorenkamp ,  Klaas Bult ,  Frank Carr ,  Christopher M. Ward ,  Ralph Duncan ,  Tom W. Kwan ,  James Y.C. Chang ,  Haideh Khorramabadi

发明人： Pieter Vorenkamp ,  Klaas Bult ,  Frank Carr ,  Christopher M. Ward ,  Ralph Duncan ,  Tom W. Kwan ,  James Y.C. Chang ,  Haideh Khorramabadi

IPC分类号： H04N5/50 ,  H04N5/44

CPC分类号： H03D3/18 ,  H01F17/0006 ,  H01F17/0013 ,  H01F27/34 ,  H01F27/40 ,  H01F27/42 ,  H01F2017/0053 ,  H01F2021/125 ,  H01L23/5227 ,  H01L27/0248 ,  H01L27/0251 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/3011 ,  H03B5/04 ,  H03B5/364 ,  H03D7/161 ,  H03D7/18 ,  H03F1/26 ,  H03F1/3211 ,  H03F3/195 ,  H03F3/45183 ,  H03F3/45188 ,  H03F3/68 ,  H03F3/72 ,  H03F2200/111 ,  H03F2200/294 ,  H03F2200/372 ,  H03F2200/447 ,  H03F2200/63 ,  H03F2203/45264 ,  H03F2203/45286 ,  H03G1/0023 ,  H03G1/0029 ,  H03G3/3052 ,  H03H7/25 ,  H03H11/04 ,  H03H11/1291 ,  H03H11/53 ,  H03H11/54 ,  H03H19/004 ,  H03J1/0075 ,  H03J3/04 ,  H03J3/08 ,  H03J3/185 ,  H03J2200/10 ,  H03L7/10 ,  H03L7/183 ,  H03L7/23 ,  H03L2207/06 ,  H01L2924/00

摘要： An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver.

摘要翻译： 描述了基本上在单个CMOS集成电路上实现的具有信道选择和图像抑制的集成接收机。 接收机前端提供可编程衰减和可编程增益低噪声放大器。 频率转换电路有利地使用集成到衬底上的LC滤波器与图像抑制混合器结合，以提供足够的图像频率抑制。 过滤器调谐和电感Q补偿温度在芯片上执行。 滤波器采用多轨螺旋电感。 使用本地振荡器调整滤波器以调整替代滤波器，以及滤波器组件值期间的频率缩放与被调谐的滤波器的频率缩放。 结合滤波，频率规划提供了额外的镜像抑制。 片上本地振荡器信号产生方法的有利选择是通过PLL带外本地振荡和通过频带本地振荡器的直接合成。 PLL中的VCO使用控制电路居中，使调谐电容范围居中。 差分晶体振荡器有利地用作频率参考。 差分信号传输有利地用于整个接收机。

公开(公告)号：US20080266749A1

公开(公告)日：2008-10-30

申请号：US11878696

申请日：2007-07-26

申请人： Victor Chiu-Kit Fong ,  Eric Bruce Blecker ,  Tom W. Kwan ,  Ning Li ,  Sumant Ranganthan ,  Chao Tang ,  Pieter Vorenkamp

发明人： Victor Chiu-Kit Fong ,  Eric Bruce Blecker ,  Tom W. Kwan ,  Ning Li ,  Sumant Ranganthan ,  Chao Tang ,  Pieter Vorenkamp

IPC分类号： H01G4/228

CPC分类号： H01L23/5223 ,  H01L23/5225 ,  H01L27/0207 ,  H01L27/0805 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to from the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance.

摘要翻译： 本发明提供了几种可扩展的集成电路高密度电容器及其布局技术。 电容器例如通过改变金属层的数量和/或从电容器使用的金属层的面积来缩放。 电容器使用不同的金属化图案来形成金属层，以及不同的通孔图案以耦合相邻的金属层。 在实施例中，可选屏蔽包括作为电容器的最顶层和/或最底层，和/或作为侧屏蔽，以减少不必要的寄生电容。

公开(公告)号：US07388905B2

公开(公告)日：2008-06-17

申请号：US11414211

申请日：2006-05-01

申请人： Pieter Vorenkamp

发明人： Pieter Vorenkamp

IPC分类号： H04B1/38

CPC分类号： H04L27/0002 ,  H04L27/2601

摘要： An ADSL transceiver chip is provided that includes an analog front-end and a digital signal processor (DSP) integrated on the same substrate. A line driver for the ADSL transceiver can be located on a separate substrate. In embodiments of the invention, the transceiver chip is implemented in a CMOS process. For example, the process could be a low voltage CMOS process. It is highly advantageous to build the analog front-end and the DSP on a single integrated IC because it allows for reduced manufacturing part count, reduced assembly time and cost. Furthermore, the line driver substrate can require a high voltage semiconductor process (e.g. 18 volts peak-to-peak) in some applications, because of the need for adequate voltage to drive the ADSL line. Whereas, the analog front-end and the DSP do not need the such a high-voltage process as required for the by the line driver 102. For example, the analog front-end and DSP can operate with 3.3 v or 5.0 v peak-to-peak. Therefore, the economies can be achieved by integrating the analog front-end and the DSP on the same substrate.

摘要翻译： 提供了ADSL收发器芯片，其包括集成在同一基板上的模拟前端和数字信号处理器（DSP）。 ADSL收发器的线路驱动器可以位于单独的基板上。 在本发明的实施例中，收发器芯片以CMOS工艺实现。 例如，该过程可以是低电压CMOS工艺。 在单个集成IC上构建模拟前端和DSP是非常有利的，因为它允许减少制造部件数量，缩短组装时间和成本。 此外，由于需要足够的电压来驱动ADSL线路，因此在某些应用中，线路驱动器基板可能需要高电压半导体工艺（例如18伏峰 - 峰）。 而模拟前端和DSP不需要线驱动器102所需的这样的高压处理。 例如，模拟前端和DSP可以在3.3V或5.0V峰峰值下工作。 因此，可以通过将模拟前端和DSP集成在同一个基板上来实现经济。