公开(公告)号：US10224221B2

公开(公告)日：2019-03-05

申请号：US15055439

申请日：2016-02-26

Applicant: Lam Research Corporation

Inventor： Harmeet Singh ,  Thorsten Lill ,  Vahid Vahedi ,  Alex Paterson ,  Monica Titus ,  Gowri Kamarthy

IPC: H01L21/3065 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/67 ,  H01J37/32

Abstract: The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. Where multiple plasma grids are used, one or more of the grids may be movable, allowing for tenability of the plasma conditions in at least the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber.

公开(公告)号：US10141163B2

公开(公告)日：2018-11-27

申请号：US15261738

申请日：2016-09-09

Applicant: Lam Research Corporation

Inventor： Thorsten Lill ,  Harmeet Singh ,  Alex Paterson ,  Gowri Kamarthy

IPC: H01J37/32

Abstract: Systems and methods controlling ion energy within a plasma chamber are described. One of the systems includes an upper electrode coupled to a sinusoidal RF generator for receiving a sinusoidal signal and a nonsinusoidal RF generator for generating a nonsinusoidal signal. The system further includes a power amplifier coupled to the nonsinusoidal RF generator. The power amplifier is used for amplifying the nonsinusoidal signal to generate an amplified signal. The system includes a filter coupled to the power amplifier. The filter is used for filtering the amplified signal using a filtering signal to generate a filtered signal. The system includes a chuck coupled to the filter. The chuck faces at least a portion of the upper electrode and includes a lower electrode. The lower electrode is used for receiving the filtered signal to facilitate achieving ion energy at the chuck to be between a lower threshold and an upper threshold.

公开(公告)号：US20160203990A1

公开(公告)日：2016-07-14

申请号：US15055439

申请日：2016-02-26

Applicant: Lam Research Corporation

Inventor： Harmeet Singh ,  Thorsten Lill ,  Vahid Vahedi ,  Alex Paterson ,  Monica Titus ,  Gowri Kamarthy

IPC: H01L21/3065 ,  H01L21/3213 ,  H01L21/311

CPC classification number: H01L21/67069 ,  H01J37/32009 ,  H01J37/32422 ,  H01J37/3244 ,  H01J37/32633 ,  H01J37/32715 ,  H01J2237/334 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32136

Abstract: The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. Where multiple plasma grids are used, one or more of the grids may be movable, allowing for tenability of the plasma conditions in at least the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber.

Abstract translation: 这里公开的实施例涉及用于蚀刻半导体衬底的改进的方法和设备。 等离子体栅格组件位于反应室中，以将室分成上部和下部子室。 等离子体栅格组件可以包括具有特定纵横比的槽的一个或多个等离子体栅格，其允许某些物质从上部子室通到下部子室。 在使用多个等离子体栅格的情况下，一个或多个栅格可以是可移动的，允许在至少下部子室中等离子体条件的稳定性。 在一些情况下，在上部子室中产生电子 - 离子等离子体。 使其通过栅格到下部子室的电子在它们通过时被冷却。 在某些情况下，这导致下部子室中的离子离子等离子体。

公开(公告)号：US09385003B1

公开(公告)日：2016-07-05

申请号：US14623144

申请日：2015-02-16

Applicant: Lam Research Corporation

Inventor： Ming-Shu Kuo ,  Qinghua Zhong ,  Helene Del Puppo ,  Ganesh Upadhyaya ,  Gowri Kamarthy

IPC: H01L21/302 ,  H01L21/3213 ,  H01J37/32 ,  H01L21/3205

CPC classification number: H01L21/32137 ,  H01J37/32009 ,  H01J37/321 ,  H01J37/32183 ,  H01J37/32449 ,  H01J37/32715 ,  H01L21/02068 ,  H01L21/0337 ,  H01L21/32055

Abstract: Systems and methods for etching a substrate include arranging a substrate including a first structure and a dummy structure in a processing chamber. The first structure is made of a material selected from a group consisting of silicon dioxide and silicon nitride. The dummy structure is made of silicon. Carrier gas is supplied to the processing chamber. Nitrogen trifluoride and molecular hydrogen gas are supplied to the processing chamber. Plasma is generated in the processing chamber. The dummy structure is etched.

Abstract translation: 用于蚀刻衬底的系统和方法包括在处理室中布置包括第一结构和虚设结构的衬底。 第一结构由选自二氧化硅和氮化硅的材料制成。 虚拟结构由硅制成。 载气被供应到处理室。 将三氟化氮和分子氢气供给到处理室。 在处理室中产生等离子体。 伪结构被蚀刻。

公开(公告)号：US20160181130A1

公开(公告)日：2016-06-23

申请号：US15055380

申请日：2016-02-26

Applicant: Lam Research Corporation

Inventor： Harmeet Singh ,  Thorsten Lill ,  Vahid Vahedi ,  Alex Paterson ,  Monica Titus ,  Gowri Kamarthy

IPC: H01L21/67 ,  H01J37/32

CPC classification number: H01L21/67069 ,  H01J37/32009 ,  H01J37/32422 ,  H01J37/3244 ,  H01J37/32633 ,  H01J37/32715 ,  H01J2237/334 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32136

Abstract: The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. Where multiple plasma grids are used, one or more of the grids may be movable, allowing for tenability of the plasma conditions in at least the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber.

公开(公告)号：US20150002018A1

公开(公告)日：2015-01-01

申请号：US13930138

申请日：2013-06-28

Applicant: Lam Research Corporation

Inventor： Thorsten Lill ,  Harmeet Singh ,  Alex Paterson ,  Gowri Kamarthy

IPC: H01J37/32

CPC classification number: H01J37/32174 ,  H01J37/32082 ,  H01J37/321 ,  H01J37/32128 ,  H01J37/32146 ,  H01J37/32422 ,  H01J37/32706

Abstract: Systems and methods controlling ion energy within a plasma chamber are described. One of the systems includes an upper electrode coupled to a sinusoidal RF generator for receiving a sinusoidal signal and a nonsinusoidal RF generator for generating a nonsinusoidal signal. The system further includes a power amplifier coupled to the nonsinusoidal RF generator. The power amplifier is used for amplifying the nonsinusoidal signal to generate an amplified signal. The system includes a filter coupled to the power amplifier. The filter is used for filtering the amplified signal using a filtering signal to generate a filtered signal. The system includes a chuck coupled to the filter. The chuck faces at least a portion of the upper electrode and includes a lower electrode. The lower electrode is used for receiving the filtered signal to facilitate achieving ion energy at the chuck to be between a lower threshold and an upper threshold.

Abstract translation: 描述了控制等离子体室内离子能量的系统和方法。 系统中的一个包括耦合到正弦RF发生器的上电极，用于接收正弦信号，以及用于产生非正弦信号的非正弦RF发生器。 该系统还包括耦合到非正弦RF发生器的功率放大器。 功率放大器用于放大非正弦信号以产生放大信号。 该系统包括耦合到功率放大器的滤波器。 滤波器用于使用滤波信号对放大的信号进行滤波以产生滤波信号。 该系统包括联接到过滤器的卡盘。 卡盘面向上电极的至少一部分并且包括下电极。 下部电极用于接收滤波后的信号，以便于在卡盘处获得离子能量，处于较低阈值和较高阈值之间。

公开(公告)号：US09589853B2

公开(公告)日：2017-03-07

申请号：US14337953

申请日：2014-07-22

Applicant: Lam Research Corporation

Inventor： Monica Titus ,  Gowri Kamarthy ,  Harmeet Singh ,  Yoshie Kimura ,  Meihua Shen ,  Baosuo Zhou ,  Yifeng Zhou ,  John Hoang

IPC: H01L21/00 ,  H01L21/3065 ,  H01L21/66 ,  H01L21/67 ,  H01L21/311

CPC classification number: H01L22/12 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/67103 ,  H01L22/20

Abstract: A method of planarizing an upper surface of a semiconductor substrate in a plasma etch chamber comprises supporting the substrate on a support surface of a substrate support assembly that includes an array of independently controlled thermal control elements therein which are operable to control the spatial and temporal temperature of the support surface of the substrate support assembly to form independently controllable heater zones which are formed to correspond to a desired temperature profile across the upper surface of the semiconductor substrate. The etch rate across the upper surface of the semiconductor substrate during plasma etching depends on a localized temperature thereof wherein the desired temperature profile is determined such that the upper surface of the semiconductor substrate is planarized within a predetermined time. The substrate is plasma etched for the predetermined time thereby planarizing the upper surface of the substrate.

Abstract translation: 在等离子体蚀刻室中平坦化半导体衬底的上表面的方法包括将衬底支撑在衬底支撑组件的支撑表面上，该衬底支撑组件包括其中独立控制的热控元件的阵列，其可操作以控制空间和时间温度 的基板支撑组件的支撑表面以形成独立可控的加热器区域，其形成为对应于横跨半导体基板的上表面的期望温度分布。 在等离子体蚀刻期间跨越半导体衬底的上表面的蚀刻速率取决于其局部温度，其中确定期望的温度分布，使得半导体衬底的上表面在预定时间内被平坦化。 将衬底等离子体蚀刻预定时间，从而平坦化衬底的上表面。

公开(公告)号：US20160086795A1

公开(公告)日：2016-03-24

申请号：US14954586

申请日：2015-11-30

Applicant: Lam Research Corporation

Inventor： Alex Paterson ,  Do Young Kim ,  Gowri Kamarthy ,  Helene Del Puppo ,  Jen-Kan Yu ,  Monica Titus ,  Radhika Mani ,  Noel Yui Sun ,  Nicolas Gani ,  Yoshie Kimura ,  Ting-Ying Chung

IPC: H01L21/027 ,  H01L21/311

CPC classification number: H01L21/0273 ,  H01J37/321 ,  H01J37/32422 ,  H01L21/28123 ,  H01L21/3065 ,  H01L21/31138 ,  H01L21/32137 ,  H01L21/76224 ,  H01L29/66795

Abstract: The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber. The ion-ion plasma may be used to advantage in a variety of etching processes.

Abstract translation: 这里公开的实施例涉及用于蚀刻半导体衬底的改进的方法和设备。 等离子体栅格组件位于反应室中，以将室分成上部和下部子室。 等离子体栅格组件可以包括具有特定纵横比的槽的一个或多个等离子体栅格，其允许某些物质从上部子室通到下部子室。 在一些情况下，在上部子室中产生电子 - 离子等离子体。 使其通过栅格到下部子室的电子在它们通过时被冷却。 在某些情况下，这导致下部子室中的离子离子等离子体。 离子离子等离子体可以用于各种蚀刻工艺中。

公开(公告)号：US09230819B2

公开(公告)日：2016-01-05

申请号：US14184491

申请日：2014-02-19

Applicant: Lam Research Corporation

Inventor： Alex Paterson ,  Do Young Kim ,  Gowri Kamarthy ,  Helene Del Puppo ,  Jen-Kan Yu ,  Monica Titus ,  Radhika Mani ,  Noel Yui Sun ,  Nicolas Gani ,  Yoshie Kimura ,  Ting-Ying Chung

IPC: H01L21/00 ,  H01L21/3065 ,  H01L21/027 ,  H01L21/3213 ,  H01J37/32 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L21/0273 ,  H01J37/321 ,  H01J37/32422 ,  H01L21/28123 ,  H01L21/3065 ,  H01L21/31138 ,  H01L21/32137 ,  H01L21/76224 ,  H01L29/66795

Abstract: The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber. The ion-ion plasma may be used to advantage in a variety of etching processes.

Abstract translation: 这里公开的实施例涉及用于蚀刻半导体衬底的改进的方法和设备。 等离子体栅格组件位于反应室中，以将室分成上部和下部子室。 等离子体栅格组件可以包括具有特定纵横比的槽的一个或多个等离子体栅格，其允许某些物质从上部子室通到下部子室。 在一些情况下，在上部子室中产生电子 - 离子等离子体。 使其通过栅格到下部子室的电子在它们通过时被冷却。 在某些情况下，这导致下部子室中的离子离子等离子体。 离子离子等离子体可以用于各种蚀刻工艺中。

公开(公告)号：US20150249016A1

公开(公告)日：2015-09-03

申请号：US14337953

申请日：2014-07-22

Applicant: Lam Research Corporation

Inventor： Monica Titus ,  Gowri Kamarthy ,  Harmeet Singh ,  Yoshie Kimura ,  Meihua Shen ,  Baosuo Zhou ,  Yifeng Zhou ,  John Hoang

IPC: H01L21/3065 ,  H01L21/66 ,  H01L21/67 ,  H01L21/306 ,  H01L21/02

CPC classification number: H01L22/12 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/67103 ,  H01L22/20

Abstract: A method of planarizing an upper surface of a semiconductor substrate in a plasma etch chamber comprises supporting the substrate on a support surface of a substrate support assembly that includes an array of independently controlled thermal control elements therein which are operable to control the spatial and temporal temperature of the support surface of the substrate support assembly to form independently controllable heater zones which are formed to correspond to a desired temperature profile across the upper surface of the semiconductor substrate. The etch rate across the upper surface of the semiconductor substrate during plasma etching depends on a localized temperature thereof wherein the desired temperature profile is determined such that the upper surface of the semiconductor substrate is planarized within a predetermined time. The substrate is plasma etched for the predetermined time thereby planarizing the upper surface of the substrate.

Abstract translation: 在等离子体蚀刻室中平坦化半导体衬底的上表面的方法包括将衬底支撑在衬底支撑组件的支撑表面上，该衬底支撑组件包括其中独立控制的热控元件的阵列，其可操作以控制空间和时间温度 的基板支撑组件的支撑表面以形成独立可控的加热器区域，其形成为对应于横跨半导体基板的上表面的期望温度分布。 在等离子体蚀刻期间跨越半导体衬底的上表面的蚀刻速率取决于其局部温度，其中确定期望的温度分布，使得半导体衬底的上表面在预定时间内被平坦化。 将衬底等离子体蚀刻预定时间，从而平坦化衬底的上表面。