公开(公告)号：US20080305582A1

公开(公告)日：2008-12-11

申请号：US11846024

申请日：2007-08-28

申请人： Raymond Albert Fillion ,  Richard Alfred Beaupre ,  Ahmed Elasser ,  Robert John Wojnarowski ,  Charles Steven Korman

发明人： Raymond Albert Fillion ,  Richard Alfred Beaupre ,  Ahmed Elasser ,  Robert John Wojnarowski ,  Charles Steven Korman

IPC分类号： H01L21/50

CPC分类号： H01L23/4821 ,  H01L23/4822 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L24/83 ,  H01L25/072 ,  H01L2224/2402 ,  H01L2224/24226 ,  H01L2224/2518 ,  H01L2224/32225 ,  H01L2224/72 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/83801 ,  H01L2224/92144 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/00

摘要： A semiconductor chip packaging structure is fabricated by using a dielectric film with two surfaces, and a power semiconductor chip with an active surface having contact pads. An adhesive layer is used to connect the first surface of the dielectric film and the active surface of the power semiconductor chip. A patterned electrically conductive layer is formed adjacent to the second surface of the film, extending through holes in the film to the contact pads.

摘要翻译： 通过使用具有两个表面的电介质膜和具有接触焊盘的有源表面的功率半导体芯片来制造半导体芯片封装结构。 使用粘合剂层来连接电介质膜的第一表面和功率半导体芯片的有源表面。 形成邻近膜的第二表面的图案化导电层，延伸穿过膜中的孔到接触垫。

公开(公告)号：US07391058B2

公开(公告)日：2008-06-24

申请号：US11168174

申请日：2005-06-27

申请人： Larry Burton Rowland ,  Ahmed Elasser

发明人： Larry Burton Rowland ,  Ahmed Elasser

IPC分类号： H01L29/15 ,  H01L31/0312

CPC分类号： H01L21/02505 ,  H01L21/02447 ,  H01L21/02529

摘要： A composite structure having a silicon carbide epitaxial layer is provided. The epitaxial layer includes at least four regions arranged vertically and defining respective interfaces, where each of the regions is characterized by a respective impurity concentration, where the impurity concentrations vary across each of the interfaces, and where each of the impurity concentrations exceeds 1×1017 cm−3 for at least one single impurity in all of the regions.

摘要翻译： 提供了具有碳化硅外延层的复合结构。 外延层包括至少四个垂直排列的区域并限定相应的界面，其中每个区域由相应的杂质浓度表征，其中杂质浓度在每个界面上变化，并且其中每个杂质浓度超过1×10 9 对于所有区域中的至少一种单一杂质，对于> 17 ±3 。

公开(公告)号：US20060289873A1

公开(公告)日：2006-12-28

申请号：US11168174

申请日：2005-06-27

申请人： Larry Rowland ,  Ahmed Elasser

发明人： Larry Rowland ,  Ahmed Elasser

IPC分类号： H01L31/0312 ,  H01L21/00

CPC分类号： H01L21/02505 ,  H01L21/02447 ,  H01L21/02529

摘要： A composite structure having a silicon carbide epitaxial layer is provided. The epitaxial layer includes at least four regions arranged vertically and defining respective interfaces, where each of the regions is characterized by a respective impurity concentration, where the impurity concentrations vary across each of the interfaces, and where each of the impurity concentrations exceeds 1×107 cm−3 for at least one single impurity in all of the regions.

摘要翻译： 提供了具有碳化硅外延层的复合结构。 外延层包括至少四个垂直排列的区域并限定相应的界面，其中每个区域由相应的杂质浓度表征，其中杂质浓度在每个界面上变化，并且其中每个杂质浓度超过1×10 9 对于所有区域中的至少一种单一杂质，> 7 -3±3 。

公开(公告)号：US06535370B1

公开(公告)日：2003-03-18

申请号：US09650528

申请日：2000-08-30

申请人： Thomas F. Papallo, Jr. ,  Ahmed Elasser ,  Richard L. Hein

发明人： Thomas F. Papallo, Jr. ,  Ahmed Elasser ,  Richard L. Hein

IPC分类号： H01H7300

CPC分类号： H02H3/0935 ,  H02H3/04 ,  H02H7/30

摘要： A method and apparatus generates an enhanced trip time curve capable of capturing both the non-sinusoidal energy and series effects. Relevant data including time, current, and energy is plotted on a three-dimensional set of axes. The resultant three-dimensional representation is useful for representing trip times for a protection device accounting for energy effects, and for determining selectivity in a multi-tier electrical distribution system.

摘要翻译： 一种方法和装置产生能够捕获非正弦能量和串联效应的增强跳闸时间曲线。 包括时间，当前和能量在内的相关数据绘制在三维轴组上。 所得到的三维表示对于表示能量效应的保护装置的跳闸时间以及用于在多层配电系统中确定选择性是有用的。

公开(公告)号：US08531027B2

公开(公告)日：2013-09-10

申请号：US12771892

申请日：2010-04-30

申请人： Arun Virupaksha Gowda ,  Ahmed Elasser ,  Satish Sivarama Gunturi

发明人： Arun Virupaksha Gowda ,  Ahmed Elasser ,  Satish Sivarama Gunturi

IPC分类号： H01L23/34

CPC分类号： H01L24/24 ,  H01L23/48 ,  H01L24/72 ,  H01L24/82 ,  H01L25/071 ,  H01L25/072 ,  H01L2224/04105 ,  H01L2224/18 ,  H01L2224/24137 ,  H01L2224/73267 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1301 ,  H01L2924/1302 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/351 ,  H02P2101/15 ,  H01L2924/00 ,  H01L2924/00014

摘要： Systems and methods for utilizing power overlay (POL) technology and semiconductor press-pack technology to produce semiconductor packages with higher reliability and power density are provided. A POL structure may interconnect semiconductor devices within a semiconductor package, and certain embodiments may be implemented to reduce the probability of damaging the semiconductor devices during the pressing of the conductive plates. In one embodiment, springs and/or spacers may be used to reduce or control the force applied by an emitter plate onto the semiconductor devices in the package. In another embodiment, the emitter plate may be recessed to exert force on the POL structure, rather than directly against the semiconductor devices. Further, in some embodiments, the conductive layer of the POL structure may be grown to function as an emitter plate, and regions of the conductive layer may be made porous to provide compliance.

摘要翻译： 提供了利用功率覆盖（POL）技术和半导体压制包技术制造具有更高可靠性和功率密度的半导体封装的系统和方法。 POL结构可以将半导体封装内的半导体器件互连，并且可以实现某些实施例以减少在压制导电板期间损坏半导体器件的可能性。 在一个实施例中，可以使用弹簧和/或间隔件来减少或控制由发射极板施加到封装中的半导体器件上的力。 在另一个实施例中，发射极板可以凹入以在POL结构上施加力而不是直接抵靠半导体器件。 此外，在一些实施例中，POL结构的导电层可以被生长以发挥发射极板的作用，并且导电层的区域可以制成多孔的以提供柔量。

公开(公告)号：US20130153953A1

公开(公告)日：2013-06-20

申请号：US13328796

申请日：2011-12-16

申请人： Ahmed Elasser ,  Arthur Stephen Daley ,  Alexey Vert ,  Stanislav I. Soloviev ,  Peter Almern Losee

发明人： Ahmed Elasser ,  Arthur Stephen Daley ,  Alexey Vert ,  Stanislav I. Soloviev ,  Peter Almern Losee

IPC分类号： H01L27/06 ,  H01L21/332

CPC分类号： H01L31/1113 ,  H01L27/0817 ,  H01L29/74

摘要： A thyristor device includes a semiconductor body and a conductive anode. The semiconductor body has a plurality of doped layers forming a plurality of dopant junctions and includes an optical thyristor, a first amplifying thyristor, and a switching thyristor. The conductive anode is disposed on a first side of the semiconductor body. The optical thyristor is configured to receive incident radiation to generate a first electric current, and the first amplifying thyristor is configured to increase the first electric current from the optical thyristor to at least a threshold current. The switching thyristor switches to the conducting state in order to conduct a second electric current from the anode and through the semiconductor body.

公开(公告)号：US20130076144A1

公开(公告)日：2013-03-28

申请号：US13246934

申请日：2011-09-28

申请人： Mohammed Agamy ,  Ahmed Elasser ,  Anthony William Galbraith ,  Maja Harfman-Todorovic

发明人： Mohammed Agamy ,  Ahmed Elasser ,  Anthony William Galbraith ,  Maja Harfman-Todorovic

IPC分类号： H02J1/00

CPC分类号： H01L31/02021 ,  Y02E10/50 ,  Y10T307/685

摘要： A system and method are provided for enabling a PV inverter to be connected to a string of series connected PV modules without exposing the inverter to elevated voltage stresses. The input voltage to the inverter is gradually built up by sequentially switching in more series PV modules. This system and method are simple to implement in both centralized and distributed PV power plants and in either case, it significantly increases the utilization of the PV inverter. The input switching elements can be implemented using a wide variety of parts including electro-mechanical switches, semiconductor switches (IGBTs, MOSFETs . . . , etc.) as well as MEMS devices depending on the current level and target cost. A mix of switches can also be used to assist in minimizing impedance of the final switching stage that remains connected during normal operation.

摘要翻译： 提供了一种系统和方法，用于使PV逆变器能够连接到一串串联的PV模块，而不会使逆变器暴露于升高的电压应力。 逆变器的输入电压通过依次切换更多串联的光伏组件逐渐建立起来。 这种系统和方法在集中和分布式光伏发电厂都很容易实现，在任何一种情况下，它显着提高了光伏逆变器的利用率。 输入开关元件可以使用包括机电开关，半导体开关（IGBT，MOSFET等）的各种部件以及取决于当前水平和目标成本的MEMS器件来实现。 还可以使用混合开关来最小化在正常操作期间保持连接的最终开关级的阻抗。

公开(公告)号：US08330299B2

公开(公告)日：2012-12-11

申请号：US13171683

申请日：2011-06-29

申请人： Robert Louis Steigerwald ,  Ahmed Elasser ,  Juan Antonio Sabate ,  Maja Harfman Todorovic ,  Mohammed Agamy

发明人： Robert Louis Steigerwald ,  Ahmed Elasser ,  Juan Antonio Sabate ,  Maja Harfman Todorovic ,  Mohammed Agamy

IPC分类号： H01H9/54

CPC分类号： H02M3/3372 ,  H02J3/383 ,  H02M3/158 ,  H02M2001/0093 ,  Y02E10/563 ,  Y10T307/944

摘要： A power generation system configured to provide direct current (DC) power to a DC link is described. The system includes a first power generation unit configured to output DC power. The system also includes a first DC to DC converter comprising an input section and an output section. The output section of the first DC to DC converter is coupled in series with the first power generation unit. The first DC to DC converter is configured to process a first portion of the DC power output by the first power generation unit and to provide an unprocessed second portion of the DC power output of the first power generation unit to the output section.

摘要翻译： 描述了被配置为向DC链路提供直流（DC）电力的发电系统。 该系统包括被配置为输出直流电力的第一发电单元。 该系统还包括第一DC-DC转换器，其包括输入部分和输出部分。 第一DC-DC转换器的输出部分与第一发电单元串联耦合。 第一DC-DC转换器被配置为处理由第一发电单元输出的直流电力的第一部分，并且向输出部提供第一发电单元的直流电力输出的未处理的第二部分。

公开(公告)号：US07829386B2

公开(公告)日：2010-11-09

申请号：US11846024

申请日：2007-08-28

申请人： Raymond Albert Fillion ,  Richard Alfred Beaupre ,  Ahmed Elasser ,  Robert John Wojnarowski ,  Charles Steven Korman

发明人： Raymond Albert Fillion ,  Richard Alfred Beaupre ,  Ahmed Elasser ,  Robert John Wojnarowski ,  Charles Steven Korman

IPC分类号： H01L21/48 ,  H01L23/34

CPC分类号： H01L23/4821 ,  H01L23/4822 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L24/83 ,  H01L25/072 ,  H01L2224/2402 ,  H01L2224/24226 ,  H01L2224/2518 ,  H01L2224/32225 ,  H01L2224/72 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/83801 ,  H01L2224/92144 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/00

摘要： A semiconductor chip packaging structure is fabricated by using a dielectric film with two surfaces, and a power semiconductor chip with an active surface having contact pads. An adhesive layer is used to connect the first surface of the dielectric film and the active surface of the power semiconductor chip. A patterned electrically conductive layer is formed adjacent to the second surface of the film, extending through holes in the film to the contact pads.

摘要翻译： 通过使用具有两个表面的电介质膜和具有接触焊盘的有源表面的功率半导体芯片来制造半导体芯片封装结构。 使用粘合剂层来连接电介质膜的第一表面和功率半导体芯片的有源表面。 形成邻近膜的第二表面的图案化导电层，延伸穿过膜中的孔到接触垫。

公开(公告)号：US07262444B2

公开(公告)日：2007-08-28

申请号：US11205903

申请日：2005-08-17

申请人： Raymond Albert Fillion ,  Richard Alfred Beaupre ,  Ahmed Elasser ,  Robert John Wojnarowski ,  Charles Steven Korman

发明人： Raymond Albert Fillion ,  Richard Alfred Beaupre ,  Ahmed Elasser ,  Robert John Wojnarowski ,  Charles Steven Korman

IPC分类号： H01L31/111 ,  H01L21/48

CPC分类号： H01L23/4822 ,  H01L23/4821 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L25/072 ,  H01L2224/2402 ,  H01L2224/24137 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/92135 ,  H01L2224/92144 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/00

摘要： A semiconductor chip packaging structure comprising a dielectric film having one or more through holes aligned with the one or more contact pads of at least one power semiconductor chip. A patterned electrically conductive layer adjacent to the dielectric film has one or more electrically conductive posts which extend through the one or more though holes aligned with the contact pads to electrically couple the conductive layer to the contact pads. In certain embodiments, one or more air gaps may be formed between the dielectric film and the active surface of the at least one power semiconductor chip. Methods for fabricating the semiconductor chip packaging structure are also disclosed.

摘要翻译： 一种半导体芯片封装结构，包括具有与至少一个功率半导体芯片的一个或多个接触焊盘对准的一个或多个通孔的电介质膜。 与电介质膜相邻的图案化导电层具有一个或多个导电柱，其延伸穿过与接触焊盘对准的一个或多个通孔，以将导电层电耦合到接触焊盘。 在某些实施例中，可以在介电膜和至少一个功率半导体芯片的有源表面之间形成一个或多个气隙。 还公开了制造半导体芯片封装结构的方法。