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11.发明申请METHOD FOR PERFORMING LOOP UNROLLED DECISION FEEDBACK EQUALIZATION IN AN ELECTRONIC DEVICE WITH AID OF VOLTAGE FEEDFORWARD, AND ASSOCIATED APPARATUS 有权在具有电压补偿的电子设备中执行环路未决决策反馈均衡的方法和相关设备公开(公告)号：US20160065397A1
公开(公告)日：2016-03-03
申请号：US14737513
申请日：2015-06-12
Applicant: MEDIATEK INC.
Inventor： Tsung-Hsin Chou , Chih-Hsien Lin , Huai-Te Wang , Bo-Jiun Chen , Yan-Bin Luo
IPC: H04L25/03
CPC classification number: H04L25/03057 , H04L25/03885 , H04L2025/03484 , H04L2025/0349 , H04L2025/03777 , H04L2025/03808
Abstract: A method for performing loop unrolled decision feedback equalization (DFE) and an associated apparatus are provided. The method includes: receiving a tap control signal and an offset control signal from a digital domain of a DFE receiver in an electronic device, and generating DFE information respectively corresponding to the tap control signal and the offset control signal in an analog domain of the DFE receiver; broadcasting the DFE information respectively corresponding to the tap control signal and the offset control signal toward comparators in the DFE receiver; utilizing the comparators to perform comparison operations according to the DFE information respectively corresponding to the tap control signal and the offset control signal to generate comparison results; and selectively adjusting the tap control signal and the offset control signal according to the comparison results, to optimize the DFE information respectively corresponding to the tap control signal and the offset control signal, respectively.
Abstract translation: 提供了一种用于执行循环展开的判决反馈均衡（DFE）和相关联的装置的方法。 该方法包括：从电子设备中的DFE接收机的数字域接收抽头控制信号和偏移控制信号，并且在DFE的模拟域中产生分别对应于抽头控制信号和偏移控制信号的DFE信息 接收器 将分别对应于抽头控制信号和偏移控制信号的DFE信息广播到DFE接收机中的比较器; 利用比较器根据分别对应于抽头控制信号和偏移控制信号的DFE信息执行比较操作，以产生比较结果; 并且根据比较结果选择性地调整抽头控制信号和偏移控制信号，分别优化分别对应于抽头控制信号和偏移控制信号的DFE信息。
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12.发明授权Method for performing phase shift control in an electronic device, and associated apparatus 有权一种用于在电子设备中执行相移控制的方法，以及相关联的装置公开(公告)号：US09246480B2
公开(公告)日：2016-01-26
申请号：US14294130
申请日：2014-06-02
Applicant: MEDIATEK INC.
Inventor： Yan-Bin Luo , Bo-Jiun Chen , Ke-Chung Wu
CPC classification number: H03K5/131 , H03K3/0322 , H03K2005/00052 , H03K2005/00058
Abstract: A method for performing phase shift control in an electronic device and an associated apparatus are provided, where the method includes: obtaining a set of clock signals corresponding to a set of phases, wherein any two phases of the set of phases are different from each other; and controlling a phase shift of an output signal of an oscillator by selectively mixing the set of clock signals into the oscillator according to a set of digital weighting control signals, wherein the phase shift corresponds to the set of digital weighting control signals, and the set of digital weighting control signals carries a set of digital weightings for selectively mixing the set of clock signals. More particularly, the method may include: selectively mixing the set of clock signals into a specific stage of a plurality of stages of the oscillator according to the set of digital weighting control signals.
Abstract translation: 提供了一种用于在电子设备和相关设备中执行相移控制的方法，其中该方法包括：获得与一组相位相对应的一组时钟信号，其中该组相位中的任何两个相位彼此不同 ; 以及通过根据一组数字加权控制信号选择性地将所述一组时钟信号混合到所述振荡器中来控制振荡器的输出信号的相移，其中所述相移对应于所述一组数字加权控制信号，并且所述组 数字加权控制信号携带一组数字加权，用于选择性地混合该组时钟信号。 更具体地说，该方法可以包括：根据该组数字加权控制信号，将该组时钟信号选择性地混合到振荡器的多个级的特定级中。
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13.发明授权Electronic device having circuit board with co-layout design of multiple connector placement sites and related circuit board thereof 有权具有电路板的电子设备，具有多个连接器放置位置的相互配置设计及其相关电路板公开(公告)号：US09183340B2
公开(公告)日：2015-11-10
申请号：US14158876
申请日：2014-01-20
Applicant: MEDIATEK INC.
Inventor： Huai-Yuan Feng , Ching-Gu Pan , Yan-Bin Luo , Hua Wu , Shang-Yi Lin
CPC classification number: G06F17/5072 , H05K1/029 , H05K1/0295 , H05K2201/09954 , H05K2201/10189 , H05K2201/10689
Abstract: An electronic device includes an integrated circuit, a connector, and a circuit board. The integrated circuit includes a first signal processing circuit, a second signal processing circuit, and an interface multiplexer having a first input port electrically connected to the first signal processing circuit, a second input port electrically connected to the second signal processing circuit, and an output port arranged to be electrically connected to the first input port or the second input port. The circuit board carries the integrated circuit and has a plurality of connector placement sites, including at least a first connector placement site each dedicated to the first signal processing circuit and at least a second connector placement site each dedicated to the second signal processing circuit. The connector placement sites and the output port of the interface multiplexer are electrically connected in series. The connector is installed on one of the connector placement sites.
Abstract translation: 电子设备包括集成电路，连接器和电路板。 集成电路包括第一信号处理电路，第二信号处理电路和接口多路复用器，其具有电连接到第一信号处理电路的第一输入端口，电连接到第二信号处理电路的第二输入端口和输出端 端口被布置成电连接到第一输入端口或第二输入端口。 电路板承载集成电路并且具有多个连接器放置位置，包括至少第一连接器放置位置，每个专用于第一信号处理电路和至少第二连接器放置位置，每个专用于第二信号处理电路。 接口多路复用器的连接器放置位置和输出端口串联电连接。 连接器安装在其中一个连接器放置位置上。
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14.发明申请ELECTRONIC DEVICE HAVING CIRCUIT BOARD WITH CO-LAYOUT DESIGN OF MULTIPLE CONNECTOR PLACEMENT SITES AND RELATED CIRCUIT BOARD THEREOF 有权具有多个连接器放置站点及其相关电路板的配套设计的电路板的电子设备公开(公告)号：US20140137065A1
公开(公告)日：2014-05-15
申请号：US14158876
申请日：2014-01-20
Applicant: MEDIATEK INC.
Inventor： Huai-Yuan Feng , Ching-Gu Pan , Yan-Bin Luo , Hua Wu , Shang-Yi Lin
IPC: G06F17/50
CPC classification number: G06F17/5072 , H05K1/029 , H05K1/0295 , H05K2201/09954 , H05K2201/10189 , H05K2201/10689
Abstract: An electronic device includes an integrated circuit, a connector, and a circuit board. The integrated circuit includes a first signal processing circuit, a second signal processing circuit, and an interface multiplexer having a first input port electrically connected to the first signal processing circuit, a second input port electrically connected to the second signal processing circuit, and an output port arranged to be electrically connected to the first input port or the second input port. The circuit board carries the integrated circuit and has a plurality of connector placement sites, including at least a first connector placement site each dedicated to the first signal processing circuit and at least a second connector placement site each dedicated to the second signal processing circuit. The connector placement sites and the output port of the interface multiplexer are electrically connected in series. The connector is installed on one of the connector placement sites.
Abstract translation: 电子设备包括集成电路，连接器和电路板。 集成电路包括第一信号处理电路，第二信号处理电路和接口多路复用器，其具有电连接到第一信号处理电路的第一输入端口，电连接到第二信号处理电路的第二输入端口和输出端 端口被布置成电连接到第一输入端口或第二输入端口。 电路板承载集成电路并且具有多个连接器放置位置，包括至少第一连接器放置位置，每个专用于第一信号处理电路和至少第二连接器放置位置，每个专用于第二信号处理电路。 接口多路复用器的连接器放置位置和输出端口串联电连接。 连接器安装在其中一个连接器放置位置上。
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公开(公告)号：US20170243690A1
公开(公告)日：2017-08-24
申请号：US15186554
申请日：2016-06-20
Applicant: MEDIATEK INC.
Inventor： Huan-Sheng Chen , Yan-Bin Luo
IPC: H01F27/28
CPC classification number: H01F27/2804 , H01F17/0006 , H01F27/346 , H01F2017/0073
Abstract: A composite inductor structure is provided, which comprises: a first spiral inductor and a second spiral inductor. The first spiral inductor has a plurality of loops and generates a first electromagnetic field, wherein an outermost loop of the first spiral inductor has a first end point, and an innermost loop of the first spiral inductor has a second end point. The second spiral inductor is arranged to be adjacent to the first spiral inductor, and has a plurality of loops and generates a second electromagnetic field, wherein an outermost loop of the second spiral inductor has a third end point, and an innermost loop of the second spiral inductor has a fourth end point, and the second spiral inductor is rotated by a specific degree with respect to an orientation of the first spiral inductor, and the first electromagnetic field and the second electromagnetic field are oppositely directed.
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Patent Agency Ranking
公开(公告)号：US09665114B2
公开(公告)日：2017-05-30
申请号：US14043859
申请日：2013-10-02
Applicant: MEDIATEK INC.
Inventor： Yan-Bin Luo , Chih-Chien Hung
Abstract: A regulator applied to regulate a first reference voltage on an output terminal, the regulator includes: a sensing circuit, arranged to sense a variation of the first reference voltage on the output terminal to generate a sensing signal; and a gain stage, arranged to provide an adjusting current to the output terminal in response to the sensing signal for reducing the variation of the first reference voltage, and the gain stage is coupled in parallel to a loading circuit powered by the first reference voltage.
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公开(公告)号：US09608798B2
公开(公告)日：2017-03-28
申请号：US15194509
申请日：2016-06-27
Applicant: MEDIATEK INC.
Inventor： Yan-Bin Luo , Bo-Jiun Chen , Ke-Chung Wu , Yi-Chieh Huang
CPC classification number: H04L7/0087 , H03F3/45475 , H03K3/0322 , H03K5/131 , H03K2005/00052 , H03K2005/00058 , H03L7/0807 , H03L7/0814 , H04L7/0331
Abstract: A method for performing phase shift control for timing recovery in an electronic device and an associated apparatus are provided, where the method includes: generating an output signal of an oscillator, wherein a phase shift of the output signal of the oscillator is controlled by selectively combining a set of clock signals into the oscillator according to a set of digital control signals, and the set of clock signals is obtained from a clock generator, wherein the phase shift corresponds to the set of digital control signals, and the set of digital control signals carries a set of digital weightings for selectively mixing the set of clock signals; and performing timing recovery and sampling on a receiver input signal of a receiver in the electronic device according to the output signal of the oscillator to reproduce data from the receiver input signal.
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18.发明授权公开(公告)号：US09590610B2
公开(公告)日：2017-03-07
申请号：US14822913
申请日：2015-08-11
Applicant: MEDIATEK INC.
Inventor： Yan-Bin Luo , Chien-Hua Wu , Chung-Shi Lin , Chih-Hsien Lin
CPC classification number: H03K17/10 , H04L25/0272 , H04L25/0282 , H04L25/4906
Abstract: A driver circuit for receiving input data and generating an output signal to a termination element is disclosed, wherein the input data has a first bit and second bit, and the driver circuit includes: a pair of differential output terminals, arranged for outputting the output signal, wherein the pair of differential output terminals has a first output terminal and a second output terminal; a current mode drive unit, coupled to the pair of differential output terminals, for outputting a current from one of the first output terminal and the second output terminal, and receiving the current from the other of the first output terminal and the second output terminal according to the first bit; and a voltage mode drive unit, coupled to the pair of differential output terminals, for providing voltages to the first output terminal and the second output terminal according to at least the second bit.
Abstract translation: 公开了一种用于接收输入数据并向终端元件产生输出信号的驱动电路，其中输入数据具有第一位和第二位，并且驱动电路包括：一对差分输出端，用于输出输出信号 ，其中所述一对差分输出端子具有第一输出端子和第二输出端子; 电流模式驱动单元，耦合到所述一对差分输出端子，用于从所述第一输出端子和所述第二输出端子之一输出电流，以及根据所述第一输出端子和所述第二输出端子中的另一个接收所述电流， 到第一位 以及耦合到所述一对差分输出端子的电压模式驱动单元，用于根据至少所述第二位向所述第一输出端子和所述第二输出端子提供电压。
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公开(公告)号：US20170054656A1
公开(公告)日：2017-02-23
申请号：US15050473
申请日：2016-02-23
Applicant: MEDIATEK INC.
Inventor： Yan-Bin Luo , Hao-Hui Yin , Chih-Ching Yu , Yao-Chun Su
IPC: H04L12/931 , H04L12/935
CPC classification number: H04L49/40 , H01L25/0655 , H01L25/18 , H01L2224/16227 , H01L2224/16235 , H01L2924/15192 , H01L2924/15311 , H03M9/00 , H04L49/30
Abstract: A multi-chip structure comprises a switch system on chip (switch SOC), a plurality of serializer/deserializer (SerDes) chips positioned around the switch SOC, and a plurality of inter-chip interfaces for connecting the switch SOC to the plurality of SerDes chips, respectively.
Abstract translation: 多芯片结构包括片上开关系统（开关SOC），位于开关SOC周围的多个串行器/解串器（SerDes）芯片，以及用于将开关SOC连接到多个SerDes的多个芯片间接口 芯片。
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20.发明授权Method for performing data sampling control in an electronic device, and associated apparatus 有权用于在电子设备中执行数据采样控制的方法和相关联的设备公开(公告)号：US09379921B2
公开(公告)日：2016-06-28
申请号：US14740264
申请日：2015-06-16
Applicant: MEDIATEK INC.
Inventor： Huai-Te Wang , Tsung-Hsin Chou , Chih-Hsien Lin , Bo-Jiun Chen , Yan-Bin Luo
CPC classification number: H04L25/03057 , H03L7/087 , H03L7/091 , H03L7/095 , H03L7/099 , H04L7/0025 , H04L7/0331
Abstract: A method for performing data sampling control in an electronic device and an associated apparatus are provided, where the method includes the steps of: detecting whether a data pattern of a received signal of a decision feedback equalizer (DFE) receiver in the electronic device matches a predetermined data pattern, to selectively trigger a data sampling time shift configuration of the DFE receiver; and when the data sampling time shift configuration is triggered, utilizing a phase shift clock, rather than a normal clock corresponding to a normal configuration of the DFE receiver, as an edge sampler clock of an edge sampler in the DFE receiver, to lock onto edge timing of the received signal, and controlling the phase shift clock and the normal clock to have different phases, respectively, to shift data sampling time of the DFE receiver, for performing data sampling in the DFE receiver.
Abstract translation: 提供了一种在电子设备和相关设备中执行数据采样控制的方法，其中该方法包括以下步骤：检测电子设备中的判决反馈均衡器（DFE）接收机的接收信号的数据模式是否匹配 预定数据模式，以选择性地触发DFE接收机的数据采样时移配置; 并且当触发数据采样时移配置时，利用相移时钟而不是与DFE接收机的正常配置对应的正常时钟作为DFE接收机中的边缘采样器的边缘采样器时钟来锁定到边缘 接收信号的定时，并且分别控制相移时钟和正常时钟以具有不同的相位，以移位DFE接收机的数据采样时间，以便在DFE接收机中执行数据采样。
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