公开(公告)号：US20230353419A1

公开(公告)日：2023-11-02

申请号：US18349148

申请日：2023-07-09

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Daniel Marcovitch ,  Idan Burstein ,  Liran Liss ,  Hillel Chapman ,  Dror Goldenberg ,  Michael Kagan ,  Aviad Yehezkel ,  Peter Paneah

IPC: H04L12/46 ,  G06F13/40 ,  G06F13/42 ,  G06F15/173

CPC classification number: H04L12/4625 ,  G06F13/4027 ,  G06F13/4208 ,  G06F15/17331 ,  H04L12/4633 ,  G06F2213/0026

Abstract: A cross-network bridging apparatus includes a bus interface and bridging circuitry. The bus interface is configured for connecting to a system bus. The bridging circuitry is configured to translate between (i) system-bus transactions that are exchanged between one or more local devices that are coupled to the system bus and served by the system bus and one or more remote processors located across a network from the apparatus, and (ii) data units that convey the system-bus transactions, for transmitting and receiving as network packets over the network to and from the remote processors.

公开(公告)号：US20230214341A1

公开(公告)日：2023-07-06

申请号：US18174668

申请日：2023-02-27

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Tzahi Oved ,  Achiad Shochat ,  Liran Liss ,  Noam Bloch ,  Aviv Heller ,  Idan Burstein ,  Ariel Shahar ,  Peter Paneah

IPC: G06F13/28 ,  G06F3/06

CPC classification number: G06F13/28 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0673 ,  G06F2213/28

Abstract: Computing apparatus includes a host computer, including multiple non-uniform memory access (NUMA) nodes, including at least first and second NUMA nodes, which include first and second local memories and first and second host bus interfaces for connection to first and second peripheral component buses, respectively. A network interface controller (NIC) is to receive a definition of a memory region extending over respective first and second parts of the first and second local memories and to receive a memory mapping with respect to the memory region that is applicable to both the first and second local memories, and to apply the memory mapping in writing data to the memory region via first and second NIC bus interfaces in a sequence of direct memory access (DMA) transactions to the respective first and second parts of the first and second local memories in response to packets received through a network port.

公开(公告)号：US11500808B1

公开(公告)日：2022-11-15

申请号：US17384834

申请日：2021-07-26

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Avraham Ganor ,  Peter Paneah ,  Dotan David Levi

IPC: G06F13/42 ,  G06F13/40 ,  G06F11/14 ,  G06F1/3234 ,  G06F9/448

Abstract: A peripheral device includes a bus interface and circuitry. The bus interface is configured to connect to a peripheral bus for communicating with a host in accordance with a peripheral-bus specification that specifies a physical reset signal asserted by the host. The circuitry is configured to execute predefined logic that evaluates a reset condition that is indicative of imminent assertion of the physical reset signal by the host, and to perform a reset procedure in response to meeting the reset condition.

公开(公告)号：US10852967B2

公开(公告)日：2020-12-01

申请号：US15963236

申请日：2018-04-26

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Ariel Shahar ,  Peter Paneah ,  Maxim Zaborov

IPC: G06F3/06 ,  G06F13/16

Abstract: Apparatuses and methods are described that provide for a mechanism for allocating physical device memory for one or more virtual functions. In particular, a memory allocating framework is provided to utilize device memory more efficiently by mapping at least one target location of the physical memory in a Base Address Register (BAR) associated with the virtual function from a plurality of available target locations based on an allocation request. The memory allocating framework is further configured to compare an indication associated with the requesting virtual function to an identifier of the requested target location. Moreover, the memory allocating framework is further configured to allow the simultaneous use of more than one virtual function at a time while providing isolation between multiple virtual functions.

公开(公告)号：US10802982B2

公开(公告)日：2020-10-13

申请号：US15947816

申请日：2018-04-08

Applicant: Mellanox Technologies, Ltd.

Inventor： Ahmad Atamlh ,  Ofir Arkin ,  Peter Paneah

IPC: G06F12/10 ,  G06F13/10 ,  G06F13/16 ,  G06F13/20 ,  G06F13/42 ,  G06F12/1081 ,  G06F13/00 ,  G06F21/85 ,  G06F21/57 ,  G06F21/55 ,  G06F21/56 ,  G06F12/14

Abstract: An apparatus includes an interface and memory acquisition circuitry. The interface is configured to communicate over a bus operating in accordance with a bus protocol, which supports address-translation transactions that translate between bus addresses in an address space of the bus and physical memory addresses in an address space of a memory. The memory acquisition circuitry is configured to read data from the memory by issuing over the bus, using the bus protocol, one or more requests that (i) specify addresses to be read in terms of the physical memory addresses, and (ii) indicate that the physical memory addresses in the requests have been translated from corresponding bus addresses even though the addresses were not obtained by any address-translation transaction over the bus.

公开(公告)号：US20240373378A1

公开(公告)日：2024-11-07

申请号：US18143509

申请日：2023-05-04

Applicant: Mellanox Technologies, Ltd.

Inventor： Natan Manevich ,  Dotan David Levi ,  Wojciech Wasko ,  Ran Ravid ,  Guy Lederman ,  Liron Mula ,  Eitan Zahavi ,  Peter Paneah

IPC: H04W56/00

Abstract: A system including a device coupled with a link and including a transmitter. The device is to generate a control block for synchronization via a physical layer of the link, the control block including a header portion of bits corresponding to a header indicating the message is a control block and a data portion of bits including synchronization information for synchronizing via the physical layer. The device is further to transmit, via the link, the control block comprising the header portion of bits and the data portion of bits.

公开(公告)号：US20240340197A1

公开(公告)日：2024-10-10

申请号：US18744636

申请日：2024-06-16

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Daniel Marcovitch ,  Idan Burstein ,  Liran Liss ,  Hillel Chapman ,  Dror Goldenberg ,  Michael Kagan ,  Aviad Yehezkel ,  Peter Paneah

IPC: H04L12/46 ,  G06F13/40 ,  G06F13/42 ,  G06F15/173

CPC classification number: H04L12/4625 ,  G06F13/4027 ,  G06F13/4208 ,  G06F15/17331 ,  H04L12/4633 ,  G06F2213/0026

Abstract: A cross-network bridging apparatus includes a bus interface and bridging circuitry. The bus interface is configured for connecting to a system bus. The bridging circuitry is configured to translate between (i) system-bus transactions that are exchanged between one or more local devices that are coupled to the system bus and served by the system bus and one or more remote processors located across a network from the apparatus, and (ii) data units that convey the system-bus transactions, for transmitting and receiving as network packets over the network to and from the remote processors.

公开(公告)号：US11750418B2

公开(公告)日：2023-09-05

申请号：US17013677

申请日：2020-09-07

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Daniel Marcovitch ,  Idan Burstein ,  Liran Liss ,  Hillel Chapman ,  Dror Goldenberg ,  Michael Kagan ,  Aviad Yehezkel ,  Peter Paneah

IPC: H04L12/46 ,  G06F13/40 ,  G06F13/42 ,  G06F15/173

CPC classification number: H04L12/4625 ,  G06F13/4027 ,  G06F13/4208 ,  G06F15/17331 ,  H04L12/4633 ,  G06F2213/0026

Abstract: A cross-network bridging apparatus includes a bus interface and bridging circuitry. The bus interface is configured for connecting to a system bus. The bridging circuitry is configured to translate between (i) system-bus transactions that are exchanged between one or more local devices that are coupled to the system bus and served by the system bus and one or more remote processors located across a network from the apparatus, and (ii) data units that convey the system-bus transactions, for transmitting and receiving as network packets over the network to and from the remote processors.

公开(公告)号：US11620245B2

公开(公告)日：2023-04-04

申请号：US17503392

申请日：2021-10-18

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Tzahi Oved ,  Achiad Shochat ,  Liran Liss ,  Noam Bloch ,  Aviv Heller ,  Idan Burstein ,  Ariel Shahar ,  Peter Paneah

IPC: G06F13/28 ,  G06F3/06

Abstract: Computing apparatus includes a host computer, including at least first and second host bus interfaces. A network interface controller (NIC) includes a network port, for connection to a packet communication network, and first and second NIC bus interfaces, which communicate via first and second peripheral component buses with the first and second host bus interfaces, respectively. Packet processing logic, in response to packets received through the network port, writes data to the host memory concurrently via both the first and second NIC bus interfaces in a sequence of direct memory access (DMA) transactions, and after writing the data in any given DMA transaction, writes a completion report to the host memory with respect to the given DMA transaction while verifying that the completion report will be available to the CPU only after all the data in the given DMA transaction have been written to the host memory.

公开(公告)号：US10394747B1

公开(公告)日：2019-08-27

申请号：US15609433

申请日：2017-05-31

Applicant: Mellanox Technologies, Ltd.

Inventor： Peter Paneah ,  Carl G. Ramey ,  Gil Moran ,  Adi Menachem ,  Christopher J. Jackson ,  Ilan Pardo ,  Ariel Shahar ,  Tzuriel Katoa

IPC: G06F13/38 ,  G06F13/40 ,  G06F13/36 ,  G06F13/42

Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores. Also disclosed are techniques for implementing hierarchical serial interconnects such as a PCI Express switch topology over a coherent mesh interconnect.