公开(公告)号：US20180234473A1

公开(公告)日：2018-08-16

申请号：US15473668

申请日：2017-03-30

Applicant: Mellanox Technologies, Ltd.

Inventor： Dotan Levi ,  Idan Burstein ,  Shlomi Museri ,  Richard Hastie

IPC: H04L29/06

Abstract: Communication apparatus includes a host interface and a network interface, which receives at least first and second redundant packet streams, each including a sequence of data packets, which include headers containing respective packet sequence numbers and data payloads of a predefined, fixed size containing respective slices of the data segment. Redundant first and second copies of each slice are transmitted in respective packets in the first and second packet streams. Packet processing circuitry receives the data packets from the network interface, maps the data packets in both the first and second packet streams, using the packet sequence numbers, to respective addresses in a buffer, and writes the data payloads to the respective addresses via the host interface while eliminating redundant data so that the buffer contains exactly one copy of each slice of the data segment, ordered in accordance with the packet sequence numbers.

公开(公告)号：US20170255559A1

公开(公告)日：2017-09-07

申请号：US15058262

申请日：2016-03-02

Applicant: Mellanox Technologies Ltd.

Inventor： Idan Burstein ,  Diego Crupnicoff ,  Shlomo Raikin ,  Michael Kagan

IPC: G06F12/08 ,  G06F13/28 ,  G06F12/12 ,  G06F13/42 ,  G06F3/06 ,  G06F15/173

Abstract: A memory device includes a target memory, having a memory address space, and a volatile buffer memory, which is coupled to receive data written over a bus to the memory device for storage in specified addresses within the memory address space. A memory controller is configured to receive, via the bus, a flush instruction and, in response to the flush instruction, to immediately flush the data held in the buffer memory with specified addresses within the memory address space to the target memory.

公开(公告)号：US20160062442A1

公开(公告)日：2016-03-03

申请号：US14836988

申请日：2015-08-27

Applicant: MELLANOX TECHNOLOGIES LTD.

Inventor： Idan Burstein ,  Shlomo Raikin ,  Noam Bloch ,  Lavi Koch

IPC: G06F1/32

CPC classification number: G06F1/3209 ,  G06F1/266 ,  G06F1/324 ,  H04L12/10 ,  Y02D10/126 ,  Y02D50/20

Abstract: A method for processing data includes receiving in a peripheral device, which is connected by a bus to a host processor having host resources, a notification of a sleep state of at least one of the host resources. While the at least one of the host resources is in the sleep state, when the peripheral device receives data from a data source for delivery to the host processor, the peripheral device sends a message to the data source, which causes the data source to defer conveying further data to the peripheral device until the at least one of the host resources has awakened from the sleep state.

Abstract translation: 一种用于处理数据的方法包括：在通过总线连接到具有主机资源的主处理器的外围设备中接收至少一个主机资源的睡眠状态的通知。 当主机资源中的至少一个处于睡眠状态时，当外围设备从数据源接收数据以传送到主处理器时，外围设备向数据源发送消息，这导致数据源延迟 将进一步的数据传送到外围设备，直到主机资源中的至少一个已经从睡眠状态唤醒。

公开(公告)号：US12259832B2

公开(公告)日：2025-03-25

申请号：US18174668

申请日：2023-02-27

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Tzahi Oved ,  Achiad Shochat ,  Liran Liss ,  Noam Bloch ,  Aviv Heller ,  Idan Burstein ,  Ariel Shahar ,  Peter Paneah

IPC: G06F13/28 ,  G06F3/06

Abstract: Computing apparatus includes a host computer, including multiple non-uniform memory access (NUMA) nodes, including at least first and second NUMA nodes, which include first and second local memories and first and second host bus interfaces for connection to first and second peripheral component buses, respectively. A network interface controller (NIC) is to receive a definition of a memory region extending over respective first and second parts of the first and second local memories and to receive a memory mapping with respect to the memory region that is applicable to both the first and second local memories, and to apply the memory mapping in writing data to the memory region via first and second NIC bus interfaces in a sequence of direct memory access (DMA) transactions to the respective first and second parts of the first and second local memories in response to packets received through a network port.

公开(公告)号：US11870590B2

公开(公告)日：2024-01-09

申请号：US17107990

申请日：2020-12-01

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Idan Burstein ,  Roee Moyal ,  Ariel Shahar ,  Noam Bloch ,  Ran Koren

IPC: H04L1/18 ,  H04L1/1829 ,  G06F15/173

CPC classification number: H04L1/1829 ,  G06F15/17331

Abstract: A method for data transfer includes transmitting a sequence of data packets from a first computer over a network to a second computer in a single RDMA data transfer transaction. Upon receipt of a second packet in the sequence without previously having received the first packet, the second computer sends a NAK packet over the network to the first computer, indicating that the first packet was not received. A retransmission mode is selected responsively to the type of the transaction, such that when the transaction is of a first type, the first packet is retransmitted from the first computer to the second computer in response to the NAK packet without retransmitting the second packet, and when the transaction is of a second type, both the first and second packets are retransmitted from the first computer to the second computer in response to the NAK packet.

公开(公告)号：US11765237B1

公开(公告)日：2023-09-19

申请号：US17724540

申请日：2022-04-20

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Liran Liss ,  Yamin Friedman ,  Michael Kagan ,  Diego Crupnicoff ,  Idan Burstein ,  Matty Kadosh ,  Tzah Oved ,  Dror Goldenberg ,  Ron Yuval Efraim ,  Alexander Eli Rosenbaum ,  Aviad Yehezkel ,  Rabia Loulou

IPC: H04L67/141 ,  H04L67/146 ,  G06F15/173 ,  H04L69/16 ,  H04L9/08

CPC classification number: H04L67/141 ,  G06F15/17331 ,  H04L9/0825 ,  H04L67/146 ,  H04L69/161

Abstract: Apparatus for data communication includes a network interface for connection to a packet data network and a host interface for connection to a host computer, which includes a central processing unit (CPU) and a host memory. Packet processing circuitry receives, via the host interface, from a kernel running on the CPU, associations between multiple remote direct memory access (RDMA) sessions and multiple different User Datagram Protocol (UDP) 5-tuple, which are assigned respectively to the RDMA sessions, and receives from an application running on the CPU a request to send an RDMA message, using a selected group of one or more of the RDMA sessions, to a peer application over the packet data network, and in response to the request, transmits, via the network interface, one or more data packets using a UDP 5-tuple that is assigned to one of the RDMA sessions in the selected group.

公开(公告)号：US20220283964A1

公开(公告)日：2022-09-08

申请号：US17189303

申请日：2021-03-02

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Idan Burstein ,  Dotan David Levi ,  Ariel Shahar ,  Lior Narkis ,  Igor Voks ,  Noam Bloch ,  Shay Aisman

IPC: G06F13/16 ,  G06F13/38 ,  G06F13/42 ,  G06F12/1045 ,  G06F15/173 ,  G06F9/46 ,  G06F9/455

Abstract: A computing system includes at least one peripheral bus, a peripheral device connected to the at least one peripheral bus, at least one memory, and first and second system components. The first system component is (i) associated with a first address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The second system component is (i) associated with a second address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The first system component is arranged to cause the peripheral device to access the second address space that is associated with the second system component.

公开(公告)号：US11327909B1

公开(公告)日：2022-05-10

申请号：US17079536

申请日：2020-10-26

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Eliav Bar-Ilan ,  Oren Duer ,  Amir Ancel ,  Yossi Kendel ,  Idan Burstein

IPC: G06F13/16 ,  G06F12/123

Abstract: In one embodiment, data communication apparatus includes a network interface including one or more ports for connection to a packet data network and configured to receive content transfer requests from at least one remote device over the network, a storage sub-system to be connected to local peripheral storage devices, and including at least one peripheral interface, and a memory sub-system including a cache and RAM, and processing circuitry to manage transfer of content between the remote device(s) and the local peripheral storage devices via the peripheral interface(s) and the cache, responsively to the content transfer requests, while pacing commencement of serving of respective ones of the content transfer requests responsively to a metric of the storage sub-system so that while ones of the content transfer requests are being served, other ones of the content transfer requests pending serving are queued in at least one pending queue.

公开(公告)号：US11102129B2

公开(公告)日：2021-08-24

申请号：US16559640

申请日：2019-09-04

Applicant: Mellanox Technologies, Ltd.

Inventor： Idan Burstein ,  Noam Bloch ,  Roee Moyal ,  Ariel Shahar ,  Yamin Friedman ,  Yuval Shpigelman

IPC: H04L12/28 ,  H04L12/801 ,  H04L12/927 ,  H04L12/863 ,  H04L29/08 ,  H04L12/841

Abstract: A network adapter includes circuitry and one or more ports. The ports connect to a communication network including multiple network elements. The circuitry accesses outbound messages that are pending to be sent over the communication network to multiple remote nodes via the ports. At least some of the outbound messages request the remote nodes to send respective amounts of data back to the network adapter. Based on the amounts of data requested by the outbound messages, the circuitry forecasts a bandwidth of inbound response traffic, which is expected to traverse a selected network element in response to the outbound messages toward the network adapter, determines a schedule for transmitting the outbound messages to the remote nodes so that the forecasted bandwidth meets a bandwidth supported by the selected network element, and transmits the outbound messages to the remote nodes in accordance with the determined schedule.

公开(公告)号：US10210125B2

公开(公告)日：2019-02-19

申请号：US15460251

申请日：2017-03-16

Applicant: Mellanox Technologies, Ltd.

Inventor： Idan Burstein

IPC: G06F13/40 ,  G06F9/54

Abstract: A method for communication includes posting in a queue a sequence of work items pointing to buffer consisting of multiple strides of a common, fixed size in a memory. A NIC receives data packets from a network containing data to be pushed to the memory. The NIC reads from the queue a first work item pointing to a first buffer and writes data from a first packet to a first number of the strides in the first buffer without consuming all of the strides in the first buffer. The NIC then writes at least a part of the data from a second packet to the remaining strides in the first buffer. When all the strides in the first buffer have been consumed, the NIC reads from the queue a second work item pointing to a second buffer, and writes further data to the strides in the second buffer.