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公开(公告)号：US10886918B2
公开(公告)日：2021-01-05
申请号：US16397797
申请日：2019-04-29
Applicant: Micron Technology, Inc.
Inventor： Jason M. Johnson
Abstract: Systems and methods for performing an efficient ZQ calibration are provided herein. The described techniques use non-linearity compensation circuitry configured to compensate for a non-linear relationship between variation in a plurality of ZQ calibration codes and corresponding resistance variations, by adjusting either: a magnitude of the adjustment to the calibration step, the ZQCODE to an alternative ZQCODE, or both the magnitude of the adjustment to the calibration step and the ZQCODE to the alternative ZQCODE.
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公开(公告)号：US20200059232A1
公开(公告)日：2020-02-20
申请号：US16397797
申请日：2019-04-29
Applicant: Micron Technology, Inc.
Inventor： Jason M. Johnson
Abstract: Systems and methods for performing an efficient ZQ calibration are provided herein. The described techniques use non-linearity compensation circuitry configured to compensate for a non-linear relationship between variation in a plurality of ZQ calibration codes and corresponding resistance variations, by adjusting either: a magnitude of the adjustment to the calibration step, the ZQCODE to an alternative ZQCODE, or both the magnitude of the adjustment to the calibration step and the ZQCODE to the alternative ZQCODE.
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公开(公告)号：US09443615B2
公开(公告)日：2016-09-13
申请号：US13693899
申请日：2012-12-04
Applicant: Micron Technology, Inc.
Inventor： Jason M. Johnson , Justin Wood , Gregory S. Hendrix , Mark D. Franklin , Daniel F. Eichenberger
CPC classification number: G11C29/40
Abstract: Apparatuses and methods for memory testing with data compression is described. An example apparatus includes a plurality of latch test circuits, wherein each of the plurality of latch test circuits is coupled to a corresponding global data line of a memory. Each of the latch test circuits is configured to receive test data and is configured to latch data from the corresponding global data line or a corresponding mask bit. Each of the plurality of latch test circuits is further configured to output data based at least in part on the corresponding mask bit. A comparison circuit is coupled to an output of each of the latch test circuits and is configured to compare output data provided by each of the latch test circuits and provide a comparator output having a logical value indicative of whether all the output data matches.
Abstract translation: 描述了使用数据压缩进行记忆测试的设备和方法。 一个示例性设备包括多个锁存测试电路，其中多个锁存测试电路中的每一个耦合到存储器的对应全局数据线。 每个锁存测试电路被配置为接收测试数据，并且被配置为从相应的全局数据线或相应的屏蔽位锁存数据。 多个锁存测试电路中的每一个进一步被配置为至少部分地基于对应的屏蔽位来输出数据。 比较电路耦合到每个锁存测试电路的输出，并且被配置为比较由每个锁存测试电路提供的输出数据，并提供具有指示所有输出数据是否匹配的逻辑值的比较器输出。
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公开(公告)号：US12079076B2
公开(公告)日：2024-09-03
申请号：US17591362
申请日：2022-02-02
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Yoshinori Fujiwara , Vivek Kotti , Christopher G. Wieduwilt , Jason M. Johnson , Kevin G. Werhane
IPC: G06F11/00 , G06F11/10 , G11C11/408 , G11C11/4096
CPC classification number: G06F11/1068 , G06F11/1032 , G06F11/1044 , G11C11/4085 , G11C11/4087 , G11C11/4096
Abstract: Apparatuses, systems, and methods for error correction. A memory device may have a number of memory cells each of which stores a bit of information. One or more error correction code (ECC) may be used to determine if the bits of information contain any errors. To mitigate the effects of failures of adjacent memory cells, the information may be divided into a first group and a second group, where each group contains information from memory cells which are non-adjacent to other memory cells of that group. Each group of information may include data bits and parity bits used to correct those data bits. For example, as part of a read operation, a first ECC circuit may receive information from even numbered memory cells, while a second ECC circuit may receive information from odd numbered memory cells.
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公开(公告)号：US20240071560A1
公开(公告)日：2024-02-29
申请号：US17822032
申请日：2022-08-24
Applicant: Micron Technology, Inc.
Inventor： Yoshinori Fujiwara , Takuya Tamano , Jason M. Johnson , Kevin G. Werhane , Daniel S. Miller
CPC classification number: G11C29/789 , G11C29/4401 , G11C29/46
Abstract: An electronic device includes multiple memory elements including multiple redundant memory elements. The electronic device also includes repair circuitry configured to remap data to the multiple memory elements when a failure occurs. The repair circuitry includes multiple fuse latches configured to implement the remapping. The repair circuitry also includes latch testing circuitry configured to test functionality of the multiple fuse latches. The latch testing circuitry includes selection circuitry configured to enable selection of a first set of fuse latches of the multiple fuse latches for a test separate from a second set of fuse latches of the multiple fuse latches that are unselected by the selection circuitry.
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Patent Agency Ranking
公开(公告)号：US20230020753A1
公开(公告)日：2023-01-19
申请号：US17305878
申请日：2021-07-16
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Yoshinori Fujiwara , Harish V. Gadamsetty , Gary Howe , Dennis G. Montierth , Michael A. Shore , Jason M. Johnson
IPC: G11C11/406 , G11C11/408 , G11C29/00 , G11C29/44
Abstract: Apparatuses, systems, and methods for refresh address masking. A memory device may refresh word lines as part of refresh operation by cycling through the word lines in a sequence. However, it may be desirable to avoid activating certain word lines (e.g., because they are defective). Refresh masking logic for each bank may include a fuse latch which stores a selected address associated with a word line to avoid. When a refresh address is generated it may be compared to the selected address. If there is a match, a refresh stop signal may be activated, which may prevent refreshing of the word line(s).
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公开(公告)号：US11538546B2
公开(公告)日：2022-12-27
申请号：US16716366
申请日：2019-12-16
Applicant: Micron Technology, Inc.
Inventor： Jason M. Johnson
Abstract: Methods, systems, and devices for data compression for global column repair are described. In some cases, a testing device may perform a first internal read operation to identify errors associated with on one or more column planes. A value (e.g., a bit) indicating whether an error occurred when testing each column plane may be stored. The testing device may perform a second internal read operation on the same column planes, or on column planes of a different bank of memory cells. The values (e.g., bits) indicating whether errors occurred during the first internal read operation and the values indicating whether errors occurred during the second internal read operation may be combined and stored in a register. The stored values may be read out (e.g., as a burst) to repair the defective column planes.
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公开(公告)号：US11264069B2
公开(公告)日：2022-03-01
申请号：US17131156
申请日：2020-12-22
Applicant: Micron Technology, Inc.
Inventor： Jason M. Johnson , Jung-Hwa Choi
IPC: G11C7/10 , G11C11/4076 , G11C11/4093 , G11C7/22 , G11C11/408
Abstract: An apparatus includes: a master die; one or more slave dies; a ZQ resister between a first node and a second node coupled to a voltage terminal; a ZQ pad coupled to each of the first node of the ZQ resister, the master die and the one or more slave dies; and a calibration channel electrically coupling the master die and the one or more slave dies, the calibration channel configured to communicate signals between the master die and the one or more slave dies for coordinating access to the ZQ pad across the master die and the one or more slave dies.
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公开(公告)号：US20220005541A1
公开(公告)日：2022-01-06
申请号：US16919922
申请日：2020-07-02
Applicant: Micron Technology, Inc.
Inventor： Jason M. Johnson , Dennis G. Montierth
Abstract: Methods of testing memory devices are disclosed. A method may include reading from a number of memory addresses of a memory array of the memory device and identifying each memory address of the number of addresses as either a pass or a fail. The method may further include storing, for each identified fail, data associated with the identified fail in a buffer of the memory device. Further, the method may include conveying, to a tester external to the memory device, at least some of the data associated with each identified fail without conveying address data associated with each identified pass to the tester. Devices and systems are also disclosed.
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公开(公告)号：US11081166B1
公开(公告)日：2021-08-03
申请号：US17000202
申请日：2020-08-21
Applicant: Micron Technology, Inc.
Inventor： Kevin G. Werhane , Jason M. Johnson , Yoshinori Fujiwara , Tyrel Z. Jensen , Daniel S. Miller , David E. Jefferson , Vivek Kotti
IPC: G11C11/408 , G11C11/22
Abstract: Methods, systems, and devices for memory device random option inversion are described. A memory device may use a second set of fuses to selectively invert options associated with a first set of fuses (e.g., blown fuses). The first set of fuses may output a first set of logic states. Option inversion logic circuitry may perform decoding based on a second set of logic states output by the second set of fuses to identify logic states of the second set of logic states that match the first set of logic states. Based on identifying the logic states, the option inversion logic circuitry may select either a logic state of the first set of logic states or an inverted logic state corresponding to the logic state, and store the selected logic state in a latch of the memory device.
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