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公开(公告)号：US20210090641A1
公开(公告)日：2021-03-25
申请号：US16581005
申请日：2019-09-24
Applicant: Micron Technology, Inc.
Inventor： Jonathan J. Strand , Sukneet Singh Basuta , Shashank Bangalore Lakshman , Jonathan D. Harms
Abstract: Methods, systems, and devices for imprint recovery for memory arrays are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.
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公开(公告)号：US20210083876A1
公开(公告)日：2021-03-18
申请号：US16573855
申请日：2019-09-17
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Jonathan D. Harms
Abstract: Computerized apparatus using characterized devices such as memories for intensive computational applications such as blockchain processing. In one embodiment, the computerized apparatus comprises a computational appliance (e.g., stand-alone box, server blade, plug-in card, or mobile device) that includes characterized memory devices. These memory devices are associated with a range of performances over a range of operational parameters, and can be used in conjunction with a solution density function to optimize memory searching. In one embodiment, the ledger appliance can communicate with other ledger appliances to create and/or use a blockchain ledger so as to facilitate decentralized exchanges between untrusted parties. In some variants, the ledger appliance may additionally use an application programming interface (API) to dynamically generate blockchains on the fly. Various other applications are also described (e.g., social media, machine learning, probabilistic applications and other error-tolerant applications).
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公开(公告)号：US20200265915A1
公开(公告)日：2020-08-20
申请号：US16276489
申请日：2019-02-14
Applicant: Micron Technology, Inc.
Inventor： Jonathan D. Harms
Abstract: Methods and apparatus for using characterized devices such as memories. In one embodiment, characterized memories are associated with a range of performances over a range of operational parameters. The characterized memories can be used in conjunction with a solution density function to optimize memory searching. In one exemplary embodiment, a cryptocurrency miner can utilize characterized memories to generate memory hard proof-of-work (POW). The results may be further validated against general compute memories; such that only valid solutions are broadcasted to the mining community. In one embodiment, the validation mechanism is implemented for a plurality of searching apparatus in parallel to provide a more distributed and efficient approach. Various other applications for characterized memories are also described in greater detail herein (e.g., blockchain, social media, machine learning, probabilistic applications and other error-tolerant applications).
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公开(公告)号：US20200264689A1
公开(公告)日：2020-08-20
申请号：US16276471
申请日：2019-02-14
Applicant: Micron Technology, Inc.
Inventor： Jonathan D. Harms
IPC: G06F1/3234 , G06F1/3225 , G06F1/3296 , G06F1/08 , G11C29/06 , G11C29/52 , G06F11/34 , G06F11/07 , G06F11/00
Abstract: Methods and apparatus for using characterized devices such as memories. In one embodiment, characterized memories are associated with a range of performances over a range of operational parameters. The characterized memories can be used in conjunction with a solution density function to optimize memory searching. In one exemplary embodiment, a cryptocurrency miner can utilize characterized memories to generate memory hard proof-of-work (POW). The results may be further validated against general compute memories; such that only valid solutions are broadcasted to the mining community. In one embodiment, the validation mechanism is implemented for a plurality of searching apparatus in parallel to provide a more distributed and efficient approach. Various other applications for characterized memories are also described in greater detail herein (e.g., blockchain, social media, machine learning, probabilistic applications and other error-tolerant applications).
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公开(公告)号：US12230546B2
公开(公告)日：2025-02-18
申请号：US17644414
申请日：2021-12-15
Applicant: Micron Technology, Inc.
Inventor： Nikolay A. Mirin , Robert Dembi , Richard T. Housley , Xiaosong Zhang , Jonathan D. Harms , Stephen J. Kramer
IPC: H01L21/66 , G03F7/00 , H01L21/302 , H01L21/68 , H01L23/544
Abstract: A method for measuring overlay between an interest level and a reference level of a wafer includes applying a magnetic field to a wafer, detecting at least one residual magnetic field emitted from at least one registration marker of a first set of registration markers within the wafer, responsive to the detected one or more residual magnetic fields, determining a location of the at least one registration marker of the first set registration markers, determining a location of at least one registration marker of a second set of registration markers, and responsive to the respective determined locations of the at least one registration marker of the first set of registration markers and the at least one registration marker of the second set of registration markers, calculating a positional offset between an interest level of the wafer and a reference level of the wafer. Related methods and systems are also disclosed.
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Patent Agency Ranking
公开(公告)号：US12211571B2
公开(公告)日：2025-01-28
申请号：US17065462
申请日：2020-10-07
Applicant: Micron Technology, Inc.
Inventor： David W. Overgaard , Andrew P. Lyle , Glen E. Hush , Timothy P. Finkbeiner , Kristopher J. Kopel , Jonathan D. Harms
Abstract: Methods, systems, and devices for on-die testing for a memory device are described. In some examples, a memory die may include processing circuitry configured to perform evaluations of the memory die based on commands or instructions received from an external device. The processing circuitry may be configured to detect failures of the memory die and transmit related indications to the external device based on the on-die detection. In some examples, the processing circuitry may be configured to communicate failure information at a finer granularity than information associated with expected or nominal behavior. Additionally or alternatively, the processing circuitry may be configured to perform operations according to an internally-generated clock signal that operates at a faster rate or speed than a clock signal from the external device. In some examples, the processing circuitry may include an analog-to-digital conversion capability for digital communication of analog characteristics internal to the memory die.
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公开(公告)号：US11847183B2
公开(公告)日：2023-12-19
申请号：US17675967
申请日：2022-02-18
Applicant: Micron Technology, Inc.
Inventor： Jonathan D. Harms
IPC: G06F1/12 , G06F17/10 , G06F1/3234 , G06F1/3225 , G06F1/3296 , G06F1/08 , G06F11/00 , G11C29/52 , G06F11/34 , G06F11/07 , G11C29/06
CPC classification number: G06F17/10 , G06F1/08 , G06F1/3225 , G06F1/3275 , G06F1/3296 , G06F11/008 , G06F11/076 , G06F11/3409 , G11C29/06 , G11C29/52
Abstract: Methods and apparatus for using characterized devices such as memories. In one embodiment, characterized memories are associated with a range of performances over a range of operational parameters. The characterized memories can be used in conjunction with a solution density function to optimize memory searching. In one exemplary embodiment, a cryptocurrency miner can utilize characterized memories to generate memory hard proof-of-work (POW). The results may be further validated against general compute memories; such that only valid solutions are broadcasted to the mining community. In one embodiment, the validation mechanism is implemented for a plurality of searching apparatus in parallel to provide a more distributed and efficient approach. Various other applications for characterized memories are also described in greater detail herein (e.g., blockchain, social media, machine learning, probabilistic applications and other error-tolerant applications).
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公开(公告)号：US20230187010A1
公开(公告)日：2023-06-15
申请号：US18084892
申请日：2022-12-20
Applicant: Micron Technology, Inc.
Inventor： Jonathan D. Harms , Jonathan J. Strand , Sukneet Singh Basuta , Shashank Bangalore Lakshman
CPC classification number: G11C29/50004 , G11C11/221 , G11C11/2275 , G11C11/2259 , G11C11/2273 , G11C11/2293 , G11C2029/5004
Abstract: Methods, systems, and devices for imprint recovery for memory cells are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.
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公开(公告)号：US11430539B2
公开(公告)日：2022-08-30
申请号：US16914927
申请日：2020-06-29
Applicant: Micron Technology, Inc.
Inventor： Troy A. Manning , Troy D. Larsen , Jonathan D. Harms , Glen E. Hush , Timothy P. Finkbeiner
Abstract: Methods, systems, and devices for modifiable repair solutions for a memory array are described to support storing repair information for a memory array within the memory array itself. A memory device may include the memory array and an on-die microprocessor, where the microprocessor may retrieve the repair information from the memory array and write the repair information to repair circuitry used for identifying defective memory addresses. The microprocessor may support techniques for identifying additional defects and updating the repair information during operation of the memory array. For example, the microprocessor may identify additional defects based on errors associated with one or more memory cells of the memory array or based on testing performed on one or more memory cells of the memory array. In some cases, a host device may identify additional defects and may notify the microprocessor of the additional defects.
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公开(公告)号：US20220108761A1
公开(公告)日：2022-04-07
申请号：US17065462
申请日：2020-10-07
Applicant: Micron Technology, Inc.
Inventor： David W. Overgaard , Andrew P. Lyle , Glen E. Hush , Timothy P. Finkbeiner , Kristopher J. Kopel , Jonathan D. Harms
Abstract: Methods, systems, and devices for on-die testing for a memory device are described. In some examples, a memory die may include processing circuitry configured to perform evaluations of the memory die based on commands or instructions received from an external device. The processing circuitry may be configured to detect failures of the memory die and transmit related indications to the external device based on the on-die detection. In some examples, the processing circuitry may be configured to communicate failure information at a finer granularity than information associated with expected or nominal behavior. Additionally or alternatively, the processing circuitry may be configured to perform operations according to an internally-generated clock signal that operates at a faster rate or speed than a clock signal from the external device. In some examples, the processing circuitry may include an analog-to-digital conversion capability for digital communication of analog characteristics internal to the memory die.
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