公开(公告)号：US20250156344A1

公开(公告)日：2025-05-15

申请号：US18908532

申请日：2024-10-07

Applicant: Micron Technology, Inc.

Inventor： John Christopher M. Sancon ,  Keun Soo Song

IPC: G06F13/16 ,  G06F1/06 ,  G06F13/42

Abstract: A memory device includes a current mirror coupled to an external resistor, wherein the current mirror is configured to provide a voltage having magnitude based on a resistance of the external resistor, and an oscillator configured to generate a clock signal having a frequency based on the voltage provided from the current mirror. The memory device further includes a counter configured to receive the clock signal and an identifier generation operation enable signal. In response to the identifier generation operation enable signal, counter is configured to provide a count value that adjust in response to the frequency of the clock signal, wherein the count value is used to assign a unique identifier for communication on a to memory module management control bus.

公开(公告)号：US20240302998A1

公开(公告)日：2024-09-12

申请号：US18608591

申请日：2024-03-18

Applicant: Micron Technology, Inc.

Inventor： Keun Soo Song ,  Hyunyoo Lee ,  Kang-Yong Kim

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0602 ,  G06F3/0673

Abstract: Methods, systems, and devices for managing address access information are described. A device may receive a command for an address of a memory array. Based on or in response to the command, the device may read a first set of tag bits from the memory array. The first set of tag bits may indicate access information for a set of addresses that includes the address. The device may determine a second set of tag bits based on the command and the address. The second set of tag bits may indicate updated access information for the address. The device may generate a codeword based on the first set of tag bits and the second set of tag bits and may store the codeword in the memory array.

公开(公告)号：US12086026B2

公开(公告)日：2024-09-10

申请号：US17654354

申请日：2022-03-10

Applicant: Micron Technology, Inc.

Inventor： Keun Soo Song ,  Kang-Yong Kim ,  Hyun Yoo Lee

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1044 ,  G06F3/0619 ,  G06F3/0629 ,  G06F3/0673

Abstract: Described apparatuses and methods provide configurable error correction code (ECC) circuitry and schemes that can utilize a shared ECC engine between multiple memory banks of a memory, including a low-power double data rate (LPDDR) memory. A memory device may include one or more dies with multiple memory banks. The configurable ECC circuitry can use an ECC engine that services a memory bank by producing ECC values based on data stored in the memory bank when data-masking functionality is enabled. When data-masking functionality is disabled, the configurable ECC circuitry can use the shared ECC engine that services at least two memory banks by producing ECC values with a larger quantity of bits based on respective data stored in the at least two memory banks. By using the shared ECC engine responsive to the data-masking functionality being disabled, the ECC functionality can provide higher data reliability with lower die area utilization.

公开(公告)号：US11621031B2

公开(公告)日：2023-04-04

申请号：US17302206

申请日：2021-04-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hyun Yoo Lee ,  Kang-Yong Kim ,  Sourabh Dhir ,  Keun Soo Song

IPC: G11C5/14 ,  G11C11/4074

Abstract: In some examples, memory die may include a selection pad, which may be coupled to a power potential. The selection pad may provide a signal to a selection control circuit, which may control a selection circuit to couple a power pad to one of multiple power rails. In some examples, a power management integrated circuit may include a selection circuit to provide one power potential to a package including a memory die when a selection signal has a logic level and another power potential when the selection signal has another logic level.

公开(公告)号：US20220406357A1

公开(公告)日：2022-12-22

申请号：US17804414

申请日：2022-05-27

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim ,  Hyun Yoo Lee ,  Keun Soo Song

IPC: G11C11/4074 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

Abstract: This document describes apparatuses and techniques for multi-rail power transition. In various aspects, a power rail controller transitions a memory circuit (e.g., of a memory die) from a first power rail to a second power rail. The power rail controller then changes a voltage of the first power rail from a first voltage to a second voltage. The power rail controller may also adjust termination impedance or a clock frequency of the memory circuit before transitioning the memory circuit to the second power rail. The power rail controller then transitions the memory circuit from the second power rail to the first power rail to enable operation of the memory circuit at the second voltage. By so doing, the power rail controller may improve the reliability of memory operations when transitioning operation of the memory circuit from the first voltage to the second voltage.

公开(公告)号：US20240361914A1

公开(公告)日：2024-10-31

申请号：US18768944

申请日：2024-07-10

Applicant: Micron Technology, Inc.

Inventor： Keun Soo Song

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0629 ,  G06F3/0673

Abstract: This document describes apparatuses and techniques for implementing data masking with pulse amplitude modulation (PAM) encoded signals of a memory circuit. In various aspects, a data mask function of a memory controller may use an unassigned or prohibited PAM signaling state for a set of data lines to indicate data masking to a memory device for a group of data bits. For example, the data mask function may alter a PAM symbol or signal level for at least one data line from a low-voltage state (L) or mid-voltage state (M) state to a high-voltage state (H), resulting in a PAM signaling state for the set of data lines that corresponds data mask indication for the group of data bits. By so doing, the data mask function may indicate data masking for the group of bits without a dedicated data mask signal line, which may enable improved per-line memory bandwidth.

公开(公告)号：US11947841B2

公开(公告)日：2024-04-02

申请号：US17586534

申请日：2022-01-27

Applicant: Micron Technology, Inc.

Inventor： Keun Soo Song ,  Hyunyoo Lee ,  Kang-Yong Kim

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0602 ,  G06F3/0673

Abstract: Methods, systems, and devices for managing address access information are described. A device may receive a command for an address of a memory array. Based on or in response to the command, the device may read a first set of tag bits from the memory array. The first set of tag bits may indicate access information for a set of addresses that includes the address. The device may determine a second set of tag bits based on the command and the address. The second set of tag bits may indicate updated access information for the address. The device may generate a codeword based on the first set of tag bits and the second set of tag bits and may store the codeword in the memory array.

公开(公告)号：US11928039B1

公开(公告)日：2024-03-12

申请号：US18051603

申请日：2022-11-01

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Kang-Yong Kim ,  Mark Kalei Hadrick ,  Keun Soo Song

IPC: G06F11/27 ,  G06F7/76 ,  G06F11/30 ,  G06F13/00 ,  G06F13/14 ,  G06F13/28 ,  G06F21/85

CPC classification number: G06F11/27 ,  G06F7/762 ,  G06F11/3041 ,  G06F13/00 ,  G06F13/14 ,  G06F13/28 ,  G06F21/85 ,  G06F2213/00 ,  G06F2213/0024

Abstract: Apparatuses and techniques for implementing a data-transfer test mode are described. The data-transfer test mode refers to a mode in which the transfer of data from an interface die to a linked die can be tested prior to connecting the interface die to the linked die. In particular, the data-transfer test mode enables the interface die to perform aspects of a write operation and output a portion of write data that is intended for the linked die. With the data-transfer test mode, testing (or debugging) of the interface die can be performed during an earlier stage in the manufacturing process before integrating the interface die into an interconnected die architecture. For example, this type of testing can be performed at a wafer level or at a single-die-package (SDP) level. In general, the data-transfer test mode can be executed independent of whether the interface die is connected to the linked die.

公开(公告)号：US11804261B2

公开(公告)日：2023-10-31

申请号：US17662325

申请日：2022-05-06

Applicant: Micron Technology, Inc.

Inventor： Keun Soo Song ,  Hyunyoo Lee ,  Kang Yong Kim

IPC: G11C11/4093 ,  G06F13/40 ,  G11C11/4076 ,  H03F3/45 ,  H03K19/00

CPC classification number: G11C11/4093 ,  G06F13/4022 ,  G11C11/4076 ,  H03F3/45 ,  H03K19/0005 ,  H03F2203/45151

Abstract: This document describes apparatuses and techniques for termination for single-ended (SE) mode operation of a memory device. In various aspects, a termination circuit can terminate an unused signal line of a differential pair to a ground or power rail using a switch element when operating in the SE mode. The termination circuit may also disconnect the unused signal line from a first input of a differential amplifier and connect a reference voltage to the first input of the differential amplifier. Based on the reference voltage, the differential amplifier amplifies an SE signal received using another signal line of the differential pair at a second input of the differential amplifier to provide a clock signal for memory operations. Thus, the termination circuit may reduce an amount by which noise associated with the unused signal line affects the differential amplifier when the memory device operates in SE mode.

公开(公告)号：US20230197129A1

公开(公告)日：2023-06-22

申请号：US17556570

申请日：2021-12-20

Applicant: Micron Technology, Inc.

Inventor： Keun Soo Song

IPC: G11C7/22 ,  G11C7/10 ,  H03L7/081

CPC classification number: G11C7/222 ,  G11C7/1069 ,  G11C7/1096 ,  H03L7/0818

Abstract: Apparatuses and techniques for operating devices with multiple differential write clock signals having different phases are described. For example, a memory controller (e.g., of a host device) can provide two differential write clock signals to a memory device over an interconnect. The two differential write clock signals may have a phase offset of approximately ninety degrees. Instead of generating its own phase-delayed write clock signals using a component (e.g., a clock divider circuit) that can enter the metastable state, the memory device can use the multiple differential write clocks signals provided by the memory controller to process memory requests.