公开(公告)号：US20220189828A1

公开(公告)日：2022-06-16

申请号：US17653219

申请日：2022-03-02

Applicant: Micron Technology, Inc.

Inventor： Kevin J. Torek

IPC: H01L21/8238 ,  H01L29/66 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/786 ,  H01L29/423 ,  H01L21/822 ,  H01L27/06 ,  H01L27/108 ,  H01L21/02 ,  H01L21/84 ,  H01L21/308

Abstract: A method of forming a semiconductor structure comprises forming an array of vertical thin film transistors. Forming the array of vertical thin film transistors comprises forming a source region, forming a channel material comprising an oxide semiconductor material over the source region, exposing the channel material to a dry etchant comprising hydrogen bromide to pattern the channel material into channel regions of adjacent vertical thin film transistor structures, forming a gate dielectric material on sidewalls of the channel regions, forming a gate electrode material adjacent to the gate dielectric material, and forming a drain region over the channel regions. Related methods of forming semiconductor structures and an array of memory cells are also disclosed.

公开(公告)号：US20220109008A1

公开(公告)日：2022-04-07

申请号：US17061852

申请日：2020-10-02

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills ,  Yi Fang Lee ,  Kevin J. Torek

IPC: H01L27/12

Abstract: Some embodiments include an integrated assembly which includes a base structure. The base structure includes a series of conductive structures which extend along a first direction. The conductive structures have steps which alternate with recessed regions along the first direction. Pillars of semiconductor material are over the steps. The semiconductor material includes at least one element selected from Group 13 of the periodic table in combination with at least one element selected from Group 16 of the periodic table. The semiconductor material may be semiconductor oxide in some applications. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20220028903A1

公开(公告)日：2022-01-27

申请号：US16934607

申请日：2020-07-21

Applicant: Micron Technology, Inc.

Inventor： Yi Fang Lee ,  Jaydip Guha ,  Lars P. Heineck ,  Kamal M. Karda ,  Si-Woo Lee ,  Terrence B. McDaniel ,  Scott E. Sills ,  Kevin J. Torek ,  Sheng-Wei Yang

IPC: H01L27/12 ,  H01L21/84

Abstract: An array of vertical transistors comprises spaced pillars of individual vertical transistors that individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. The upper source/drain region comprises a conductor oxide material in individual of the pillars. The channel region comprises an oxide semiconductor material in the individual pillars. The lower source/drain region comprises a first conductive oxide material in the individual pillars atop and directly against a second conductive oxide material in the individual pillars. Horizontally-elongated and spaced conductor lines individually interconnect a respective multiple of the vertical transistors in a column direction. The conductor lines individually comprise the second conductive oxide material atop and directly against metal material. The first conductive oxide material, the second conductive oxide material, and the metal material comprise different compositions relative one another. The second conductive oxide material of the conductor lines is below and directly against the second conductive oxide material of the lower source/drain region of the individual pillars of the respective multiple vertical transistors. Horizontally-elongated and spaced conductive gate lines are individually operatively aside the oxide semiconductor material of the channel region of the individual pillars and individually interconnect a respective plurality of the vertical transistors in a row direction. A conductive structure is laterally-between and spaced from immediately-adjacent of the spaced conductor lines in the row direction. The conductive structures individually comprise a top surface that is higher than a top surface of the metal material of the conductor lines. Other embodiments, including method, are disclosed.

公开(公告)号：US10714400B2

公开(公告)日：2020-07-14

申请号：US16114614

申请日：2018-08-28

Applicant: Micron Technology, Inc.

Inventor： Kevin J. Torek

IPC: H01L21/84 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/786 ,  H01L29/423 ,  H01L21/822 ,  H01L27/06 ,  H01L27/108 ,  H01L21/02 ,  H01L21/308

Abstract: A method of forming a semiconductor structure comprises forming an array of vertical thin film transistors. Forming the array of vertical thin film transistors comprises forming a source region, forming a channel material comprising an oxide semiconductor material over the source region, exposing the channel material to a dry etchant comprising hydrogen bromide to pattern the channel material into channel regions of adjacent vertical thin film transistor structures, forming a gate dielectric material on sidewalls of the channel regions, forming a gate electrode material adjacent to the gate dielectric material, and forming a drain region over the channel regions. Related methods of forming semiconductor structures and an array of memory cells are also disclosed.

公开(公告)号：US20240429104A1

公开(公告)日：2024-12-26

申请号：US18825972

申请日：2024-09-05

Applicant: Micron Technology, Inc.

Inventor： Kevin J. Torek

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/308 ,  H01L21/822 ,  H01L21/84 ,  H01L27/06 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H10B12/00

Abstract: A method of forming a semiconductor structure comprises forming an array of vertical thin film transistors. Forming the array of vertical thin film transistors comprises forming a source region, forming a channel material comprising an oxide semiconductor material over the source region, exposing the channel material to a dry etchant comprising hydrogen bromide to pattern the channel material into channel regions of adjacent vertical thin film transistor structures, forming a gate dielectric material on sidewalls of the channel regions, forming a gate electrode material adjacent to the gate dielectric material, and forming a drain region over the channel regions. Related methods of forming semiconductor structures and an array of memory cells are also disclosed.

公开(公告)号：US11276613B2

公开(公告)日：2022-03-15

申请号：US16917379

申请日：2020-06-30

Applicant: Micron Technology, Inc.

Inventor： Kevin J. Torek

IPC: H01L21/84 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/786 ,  H01L29/423 ,  H01L21/822 ,  H01L27/06 ,  H01L27/108 ,  H01L21/02 ,  H01L21/308

Abstract: A method of forming a semiconductor structure comprises forming an array of vertical thin film transistors. Forming the array of vertical thin film transistors comprises forming a source region, forming a channel material comprising an oxide semiconductor material over the source region, exposing the channel material to a dry etchant comprising hydrogen bromide to pattern the channel material into channel regions of adjacent vertical thin film transistor structures, forming a gate dielectric material on sidewalls of the channel regions, forming a gate electrode material adjacent to the gate dielectric material, and forming a drain region over the channel regions. Related methods of forming semiconductor structures and an array of memory cells are also disclosed.

公开(公告)号：US20140370684A1

公开(公告)日：2014-12-18

申请号：US13918065

申请日：2013-06-14

Applicant: Micron Technology, Inc.

Inventor： Ranjan Khurana ,  Michael Hyatt ,  Scott L. Light ,  Kevin J. Torek ,  Anton J. deVilliers

IPC: H01L21/768 ,  H01L49/02

CPC classification number: H01L21/76816 ,  G03F7/0035 ,  G03F7/095 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L28/90

Abstract: Methods of forming semiconductor devices and features in semiconductor device structures include conducting an anti-spacer process to remove portions of a first mask material to form first openings extending in a first direction. Another anti-spacer process is conducted to remove portions of the first mask material to form second openings extending in a second direction at an angle to the first direction. Portions of the second mask material underlying the first mask material at intersections of the first openings and second openings are removed to form holes in the second mask material and to expose a substrate underlying the second mask material.

Abstract translation: 在半导体器件结构中形成半导体器件和特征的方法包括进行防间隔工艺以去除第一掩模材料的部分以形成沿第一方向延伸的第一开口。 进行另一个防间隔处理以去除第一掩模材料的部分，以形成沿与第一方向成角度的第二方向延伸的第二开口。 去除在第一开口和第二开口的交叉点处的第一掩模材料下面的第二掩模材料的部分，以在第二掩模材料中形成孔并暴露第二掩模材料下面的衬底。

公开(公告)号：US08889558B2

公开(公告)日：2014-11-18

申请号：US13712820

申请日：2012-12-12

Applicant: Micron Technology, Inc.

Inventor： Ranjan Khurana ,  Anton J. deVillers ,  Kevin J. Torek ,  Shane J. Trapp ,  Scott L. Light ,  James M. Buntin

IPC: H01L21/308 ,  B44C1/22 ,  H01L21/302

CPC classification number: H01L21/3086 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/22 ,  H01L21/266 ,  H01L21/302 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32 ,  H01L21/76816

Abstract: A method of forming a pattern on a substrate includes forming openings in material of a substrate. The openings are widened to join with immediately adjacent of the openings to form spaced pillars comprising the material after the widening. Other embodiments are disclosed.

Abstract translation: 在衬底上形成图案的方法包括在衬底的材料中形成开口。 开口被加宽以与紧邻的开口接合以在扩宽之后形成包括材料的间隔柱。 公开了其他实施例。

公开(公告)号：US20140120684A1

公开(公告)日：2014-05-01

申请号：US14147895

申请日：2014-01-06

Applicant: Micron Technology, Inc.

Inventor： Gurpreet Lugani ,  Kevin J. Torek

IPC: H01L49/02

CPC classification number: H01L27/10852 ,  H01G4/005 ,  H01G4/008 ,  H01G4/06 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/32137 ,  H01L27/10894 ,  H01L28/40 ,  H01L28/60 ,  H01L28/75 ,  H01L28/91

Abstract: A method of forming capacitors includes providing first capacitor electrodes within support material. The first capacitor electrodes contain TiN and the support material contains polysilicon. The polysilicon-containing support material is dry isotropically etched selectively relative to the TiN-containing first capacitor electrodes using a sulfur and fluorine-containing etching chemistry. A capacitor dielectric is formed over sidewalls of the first capacitor electrodes and a second capacitor electrode is formed over the capacitor dielectric. Additional methods are disclosed.

Abstract translation: 形成电容器的方法包括在支撑材料内提供第一电容器电极。 第一电容器电极含有TiN，载体材料含有多晶硅。 使用含硫和含氟蚀刻化学法，相对于含TiN的第一电容器电极，选择性地对含多晶硅的支撑材料进行干式各向异性蚀刻。 在第一电容器电极的侧壁上形成电容器电介质，并且在电容器电介质上形成第二电容器电极。 公开了另外的方法。

公开(公告)号：US12100629B2

公开(公告)日：2024-09-24

申请号：US17653219

申请日：2022-03-02

Applicant: Micron Technology, Inc.

Inventor： Kevin J. Torek

IPC: H01L21/82 ,  H01L21/02 ,  H01L21/308 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/06 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H10B12/00

CPC classification number: H01L21/823885 ,  H01L21/02565 ,  H01L21/308 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42384 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/7869 ,  H01L29/78696 ,  H10B12/05 ,  H10B12/315 ,  H10B12/50

Abstract: A method of forming a semiconductor structure comprises forming an array of vertical thin film transistors. Forming the array of vertical thin film transistors comprises forming a source region, forming a channel material comprising an oxide semiconductor material over the source region, exposing the channel material to a dry etchant comprising hydrogen bromide to pattern the channel material into channel regions of adjacent vertical thin film transistor structures, forming a gate dielectric material on sidewalls of the channel regions, forming a gate electrode material adjacent to the gate dielectric material, and forming a drain region over the channel regions. Related methods of forming semiconductor structures and an array of memory cells are also disclosed.