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    Chemistry and Compositions for Manufacturing Integrated Circuits
    11.
    发明申请
    Chemistry and Compositions for Manufacturing Integrated Circuits 审中-公开
    制造集成电路的化学和组成

    公开(公告)号：US20140264152A1

    公开(公告)日：2014-09-18

    申请号：US14290832

    申请日：2014-05-29

    Applicant: Micron Technology, Inc.

    Inventor： Aaron R. Wilson ,  Mark Kiehlbauch

    IPC: C09K13/00

    CPC classification number: C09K13/00 ,  H01L21/31122

    Abstract: In the manufacture of integrated circuits, reactive compositions that include a reactive etchant species and an oxygen-containing species can provide selective removal of target material and can reduce contamination of gas delivery lines.

    Abstract translation: 在集成电路的制造中，包括反应性蚀刻剂物质和含氧物质的反应性组合物可以提供目标材料的选择性去除并且可以减少气体输送管线的污染。

    PLASMA PROCESSING WITH PREIONIZED AND PREDISSOCIATED TUNING GASES AND ASSOCIATED SYSTEMS AND METHODS
    12.
    发明申请
    PLASMA PROCESSING WITH PREIONIZED AND PREDISSOCIATED TUNING GASES AND ASSOCIATED SYSTEMS AND METHODS 有权
    具有预先和预先调节的调谐气体和相关系统和方法的等离子体处理

    公开(公告)号：US20140238955A1

    公开(公告)日：2014-08-28

    申请号：US14272928

    申请日：2014-05-08

    Applicant: Micron Technology, Inc.

    Inventor： Mark Kiehlbauch

    IPC: B81C1/00

    CPC classification number: H01J37/32009 ,  B81C1/00531 ,  C23C16/45521 ,  H01J37/32449 ,  H01J37/32541 ,  H01J37/32577 ,  H01J37/32715

    Abstract: Plasma processing systems and methods for using pre-dissociated and/or pre-ionized tuning gases are disclosed herein. In one embodiment, a plasma processing system includes a reaction chamber, a support element in the reaction chamber, and one or more cathode discharge assemblies in the reaction chamber. The reaction chamber is configured to produce a plasma in an interior volume of the chamber. The support element positions a microelectronic workpiece in the reaction chamber, and the cathode discharge assembly supplies an at least partially dissociated and/or ionized tuning gas to the workpiece in the chamber.

    Abstract translation: 本文公开了等离子体处理系统和用于使用预分解和/或预电离调谐气体的方法。 在一个实施例中，等离子体处理系统包括反应室，反应室中的支撑元件和反应室中的一个或多个阴极排出组件。 反应室被配置为在室的内部空间中产生等离子体。 支撑元件将微电子工件定位在反应室中，并且阴极排出组件将至少部分解离和/或离子化的调谐气体提供给腔室中的工件。

    Plasma processing with preionized and predissociated tuning gases and associated systems and methods
    14.
    发明授权
    Plasma processing with preionized and predissociated tuning gases and associated systems and methods 有权
    具有预分解和预分解调谐气体的等离子体处理及相关系统和方法

    公开(公告)号：US09090460B2

    公开(公告)日：2015-07-28

    申请号：US14272928

    申请日：2014-05-08

    Applicant: Micron Technology, Inc.

    Inventor： Mark Kiehlbauch

    IPC: H01J37/32 ,  C23C16/455 ,  B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  B81C1/00

    CPC classification number: H01J37/32009 ,  B81C1/00531 ,  C23C16/45521 ,  H01J37/32449 ,  H01J37/32541 ,  H01J37/32577 ,  H01J37/32715

    Abstract: Plasma processing systems and methods for using pre-dissociated and/or pre-ionized tuning gases are disclosed herein. In one embodiment, a plasma processing system includes a reaction chamber, a support element in the reaction chamber, and one or more cathode discharge assemblies in the reaction chamber. The reaction chamber is configured to produce a plasma in an interior volume of the chamber. The support element positions a microelectronic workpiece in the reaction chamber, and the cathode discharge assembly supplies an at least partially dissociated and/or ionized tuning gas to the workpiece in the chamber.

    Abstract translation: 本文公开了等离子体处理系统和用于使用预分解和/或预电离调谐气体的方法。 在一个实施例中，等离子体处理系统包括反应室，反应室中的支撑元件和反应室中的一个或多个阴极排出组件。 反应室被配置为在室的内部空间中产生等离子体。 支撑元件将微电子工件定位在反应室中，并且阴极排出组件将至少部分解离和/或离子化的调谐气体提供给腔室中的工件。

    Apparatus and methods for capacitively coupled plasma vapor processing of semiconductor wafers
    16.
    发明授权
    Apparatus and methods for capacitively coupled plasma vapor processing of semiconductor wafers 有权
    半导体晶片电容耦合等离子体蒸汽处理的装置和方法

    公开(公告)号：US08910591B2

    公开(公告)日：2014-12-16

    申请号：US13767526

    申请日：2013-02-14

    Applicant: Micron Technology, Inc.

    Inventor： Mark Kiehlbauch

    IPC: H01L21/00 ,  C23C16/00 ,  H01J1/13 ,  H01J37/32 ,  H01L21/67

    CPC classification number: H01J1/135 ,  H01J37/32091 ,  H01J37/32724 ,  H01L21/67069 ,  H01L21/67109

    Abstract: A capacitively coupled plasma reactor comprising a processing chamber, a first electrode, a second electrode and a thermoelectric unit. The processing chamber has an upper portion with a gas inlet and a lower portion, and the upper portion is in fluid communication with the lower portion. The first electrode has a front side and a backside and is positioned at the upper portion of the processing chamber. The second electrode is positioned in the lower portion of the processing chamber and is spaced apart from the front side of the first electrode. The thermoelectric unit is positioned proximate to the backside of the first electrode and is capable of heating and cooling the first electrode.

    Abstract translation: 一种电容耦合等离子体反应器，包括处理室，第一电极，第二电极和热电单元。 处理室具有上部，其具有气体入口和下部，并且上部与下部流体连通。 第一电极具有前侧和后侧，并且位于处理室的上部。 第二电极位于处理室的下部并且与第一电极的前侧间隔开。 热电单元位于第一电极的后侧附近并且能够加热和冷却第一电极。

    Capacitor forming methods
    17.
    发明授权
    Capacitor forming methods 有权
    电容器形成方法

    公开(公告)号：US08734656B2

    公开(公告)日：2014-05-27

    申请号：US13753135

    申请日：2013-01-29

    Applicant: Micron Technology, Inc.

    Inventor： Mark Kiehlbauch

    IPC: H01G13/00

    CPC classification number: H01L28/60 ,  H01G4/33 ,  H01G13/00 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/91

    Abstract: A capacitor forming method includes forming an electrically conductive support material over a substrate, forming an opening through at least the support material to the substrate, and, after forming the opening, forming a capacitor structure contacting the substrate and the support material in the opening. The support material contains at least 25 at % carbon. Another capacitor forming method includes forming a support material over a substrate, forming an opening through at least the support material to the substrate, and, after forming the opening, forming a capacitor structure contacting the substrate and the support material in the opening. The support material contains at least 20 at % carbon. The support material has a thickness and the opening has an aspect ratio 20:1 or greater within the thickness of the support material.

    Abstract translation: 电容器形成方法包括在衬底上形成导电支撑材料，通过至少所述支撑材料形成到所述衬底的开口，并且在形成所述开口之后，形成接触所述衬底和所述开口中的所述支撑材料的电容器结构。 载体材料含有至少25原子％的碳。 另一种电容器形成方法包括在衬底上形成支撑材料，通过至少支撑材料形成到衬底的开口，并且在形成开口之后，形成接触衬底和开口中的支撑材料的电容器结构。 载体材料含有至少20原子％的碳。 支撑材料具有厚度，并且开口在支撑材料的厚度内具有20:1或更大的纵横比。

    Capacitor Forming Methods
    18.
    发明申请
    Capacitor Forming Methods 有权

    公开(公告)号：US20130140271A1

    公开(公告)日：2013-06-06

    申请号：US13753135

    申请日：2013-01-29

    Applicant: Micron Technology, Inc.

    Inventor： Mark Kiehlbauch

    IPC: H01G13/00

    CPC classification number: H01L28/60 ,  H01G4/33 ,  H01G13/00 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/91

    Abstract: A capacitor forming method includes forming an electrically conductive support material over a substrate, forming an opening through at least the support material to the substrate, and, after forming the opening, forming a capacitor structure contacting the substrate and the support material in the opening. The support material contains at least 25 at % carbon. Another capacitor forming method includes forming a support material over a substrate, forming an opening through at least the support material to the substrate, and, after forming the opening, forming a capacitor structure contacting the substrate and the support material in the opening. The support material contains at least 20 at % carbon. The support material has a thickness and the opening has an aspect ratio 20:1 or greater within the thickness of the support material.

    Semiconductor Constructions, and Semiconductor Processing Methods
    19.
    发明申请
    Semiconductor Constructions, and Semiconductor Processing Methods 有权

    公开(公告)号：US20210043631A1

    公开(公告)日：2021-02-11

    申请号：US17077242

    申请日：2020-10-22

    Applicant: Micron Technology, Inc.

    Inventor： Mark Kiehlbauch

    IPC: H01L27/108 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/78 ,  H01L23/528 ,  H01L23/535

    Abstract: Some embodiments include methods in which a pair of spaced-apart adjacent features is formed over a substrate. The features have silicon dioxide surfaces. Silicon nitride is deposited between the features. A first region of the silicon nitride is protected with a mask while a second region is not. The second region is removed to form an opening between the features. Some embodiments include semiconductor constructions that contain a pair of spaced-apart adjacent features. The features are lines extending along a first direction and are spaced from one another by a trench. Alternating plugs and intervening materials are within the trench, with the plugs and intervening materials alternating along the first direction. The intervening materials consist of silicon nitride, and the plugs have lateral peripheries that directly contact silicon dioxide of the features, and that directly contact silicon nitride of the intervening regions.

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