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    COARSE AND FINE PROGRAMMING IN A SOLID STATE MEMORY
    11.
    发明申请
    COARSE AND FINE PROGRAMMING IN A SOLID STATE MEMORY 有权
    在固态存储器中的粗略和精细编程

    公开(公告)号：US20130201759A1

    公开(公告)日：2013-08-08

    申请号：US13796602

    申请日：2013-03-12

    Applicant: Micron Technology, Inc.

    Inventor： Frankie F. Roohparvar ,  Vishal Sarin ,  Jung-Sheng Hoei

    IPC: G11C16/10

    CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/3418

    Abstract: Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes initially programming a cell with a coarse programming pulse to move its threshold voltage in a large step close to the programmed state. The neighboring cells are then programmed using coarse programming. The algorithm then returns to the initially programmed cells that are then programmed with one or more fine pulses that slowly move the threshold voltage in smaller steps to the final programmed state threshold voltage.

    Abstract translation: 适于接收和发送表示两个或多个位的位模式的模拟数据信号的存储器件有助于相对于传送指示各个位的数据信号的器件的数据传输速率的增加。 这种存储器件的编程包括：用粗略的编程脉冲对单元进行初始编程，使其阈值电压以接近编程状态的大步进移动。 然后使用粗略编程对相邻单元进行编程。 然后，该算法返回到初始编程的单元，然后使用一个或多个精细脉冲编程，该精细脉冲以较小步长将阈值电压缓慢移动到最终编程状态阈值电压。

    MEMORY DEVICES FOR PATTERN MATCHING
    12.
    发明申请
    MEMORY DEVICES FOR PATTERN MATCHING 有权

    公开(公告)号：US20220122665A1

    公开(公告)日：2022-04-21

    申请号：US17542562

    申请日：2021-12-06

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Luca De Santis ,  Tommaso Vali ,  Kenneth J. Eldredge ,  Vishal Sarin

    IPC: G11C15/04 ,  G11C16/10 ,  G11C16/04 ,  H01L27/00 ,  G11C13/06

    Abstract: Memory devices might include a plurality of memory cell pairs each configured to be programmed to store a digit of data; and control circuitry configured to cause the memory device to compare the stored digit of data of each memory cell pair to a received digit of data, determine whether a match condition or a no-match condition is indicated between the stored digit of data of each memory cell pair and the received digit of data, and deem a match condition to be met between the received digit of data and the stored digits of data of the plurality of memory cell pairs in response to a match condition being determined for a majority of memory cell pairs of the plurality of memory cell pairs.

    Threshold voltage compensation in a memory
    15.
    发明授权
    Threshold voltage compensation in a memory 有权
    存储器中的阈值电压补偿

    公开(公告)号：US09520183B2

    公开(公告)日：2016-12-13

    申请号：US14707684

    申请日：2015-05-08

    Applicant: Micron Technology, Inc.

    Inventor： Violante Moschiano ,  Tommaso Vali ,  Giovanni Naso ,  Vishal Sarin ,  William Henry Radke ,  Theodore T. Pekny

    IPC: G11C11/34 ,  G11C16/04 ,  G11C11/56 ,  G11C16/34 ,  G11C16/24 ,  G11C16/26

    CPC classification number: G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2211/5641

    Abstract: Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed “aggressor” memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation.

    Abstract translation: 电荷存储存储器中的阈值电压由阈值电压放置来控制，例如提供更可靠的操作并减少诸如相邻电荷存储元件和寄生耦合的因素的影响。 相邻编程的“侵略者”存储器单元的阈值电压的预补偿或后补偿降低了闪存系统中的阈值电压不确定性。 使用具有诸如查找表之类的数据结构的缓冲器提供了可编程的阈值电压分布，使得能够定制多级单元闪存中的数据状态的分布，例如提供更可靠的操作。

    SENSING OPERATIONS IN A MEMORY DEVICE
    17.
    发明申请
    SENSING OPERATIONS IN A MEMORY DEVICE 有权
    感应器中的感应操作

    公开(公告)号：US20150355849A1

    公开(公告)日：2015-12-10

    申请号：US14827371

    申请日：2015-08-17

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Jonathan Pabustan ,  Vishal Sarin ,  Dzung H. Nguyen

    IPC: G06F3/06 ,  G11C16/34 ,  G11C16/32 ,  G11C16/08

    CPC classification number: G06F3/0613 ,  G06F3/0655 ,  G06F3/0679 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3454 ,  G11C16/3459

    Abstract: Methods for sensing, method for programming, memory devices, and memory systems are disclosed. In one such method for sensing, a counting circuit generates a count output and a translated count output. The count output is converted into a time varying voltage that biases a word line coupled to memory cells being sensed. Target data for each memory cell is stored in a data cache associated with that particular memory cell. When it is detected that a memory cell has turned on, the translated count output associated with the count output that is indicative of the voltage level that turned on the memory cell is compared to the target data. The comparison determines the state of the memory cell.

    Abstract translation: 公开了感测方法，编程方法，存储器件和存储器系统。 在一种用于感测的方法中，计数电路产生计数输出和转换计数输出。 计数输出被转换成时变电压，该电压偏置耦合到被感测的存储器单元的字线。 每个存储器单元的目标数据被存储在与该特定存储器单元相关联的数据高速缓存器中。 当检测到存储器单元已经接通时，将与指示存储器单元接通的电压电平的计数输出相关联的转换计数输出与目标数据进行比较。 比较确定存储单元的状态。

    TWO-PART PROGRAMMING METHODS
    18.
    发明申请
    TWO-PART PROGRAMMING METHODS 有权
    两部分编程方法

    公开(公告)号：US20150262657A1

    公开(公告)日：2015-09-17

    申请号：US14725749

    申请日：2015-05-29

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Vishal Sarin ,  Allahyar Vahidimowlavi

    IPC: G11C11/56 ,  G11C16/34

    CPC classification number: G11C11/5628 ,  G11C16/0408 ,  G11C16/0458 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2211/562 ,  G11C2211/5622 ,  G11C2211/5642 ,  G11C2211/5648

    Abstract: Programming a memory in two parts to reduce cell disturb is disclosed. In at least one embodiment, data is programmed in two or more sequences of programming pulses with data requiring higher programming voltages programmed first. During each programming sequence, the data which is not being currently selected for programming is inhibited. Overlapping levels and/or voltage ranges can be used.

    Abstract translation: 公开了两部分编程存储器以减少电池干扰。 在至少一个实施例中，数据以两个或更多个编程脉冲序列编程，其中首先编程需要更高编程电压的数据。 在每个编程序列期间，禁止当前未选择编程的数据。 可以使用重叠电平和/或电压范围。

    THRESHOLD VOLTAGE COMPENSATION IN A MEMORY
    19.
    发明申请
    THRESHOLD VOLTAGE COMPENSATION IN A MEMORY 有权
    存储器中的阈值电压补偿

    公开(公告)号：US20150243351A1

    公开(公告)日：2015-08-27

    申请号：US14707684

    申请日：2015-05-08

    Applicant: Micron Technology, Inc.

    Inventor： Violante Moschiano ,  Tommaso Vali ,  Giovanni Naso ,  Vishal Sarin ,  William Henry Radke ,  Theodore T. Pekny

    IPC: G11C11/56

    CPC classification number: G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2211/5641

    Abstract: Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed “aggressor” memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation.

    Abstract translation: 电荷存储存储器中的阈值电压由阈值电压放置来控制，例如提供更可靠的操作并减少诸如相邻电荷存储元件和寄生耦合的因素的影响。 相邻编程的“侵略者”存储器单元的阈值电压的预补偿或后补偿降低了闪存系统中的阈值电压不确定性。 使用具有诸如查找表之类的数据结构的缓冲器提供了可编程的阈值电压分布，使得能够定制多级单元闪存中的数据状态的分布，例如提供更可靠的操作。

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