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    SELECTION OF AN OPTIMAL SINGLE LEVEL CELL PROGRAMMING SCHEME
    13.
    发明申请
    SELECTION OF AN OPTIMAL SINGLE LEVEL CELL PROGRAMMING SCHEME 有权

    公开(公告)号：US20250022515A1

    公开(公告)日：2025-01-16

    申请号：US18767584

    申请日：2024-07-09

    Applicant: Micron Technology, Inc.

    Inventor： Yu-Chung LIEN ,  Dheeraj SRINIVASAN ,  Michael G. MILLER ,  Zhenming ZHOU

    IPC: G11C16/10 ,  G11C16/34

    Abstract: In some implementations, a memory device may receive, from a host device, a program command. The memory device may determine that the program command is associated with a single level cell (SLC) program command. The memory device may determine a size of host data associated with the program command. The memory device may select a programming scheme, from multiple candidate programming schemes, to be used to write the host data to a memory based on the size of the host data and based on determining that the program command is associated with the SLC program command. The memory device may write the host data to the memory using the programming scheme.

    DETECTING A MEMORY WRITE RELIABILITY RISK WITHOUT USING A WRITE VERIFY OPERATION
    14.
    发明申请
    DETECTING A MEMORY WRITE RELIABILITY RISK WITHOUT USING A WRITE VERIFY OPERATION 有权

    公开(公告)号：US20240420783A1

    公开(公告)日：2024-12-19

    申请号：US18820480

    申请日：2024-08-30

    Applicant: Micron Technology, Inc.

    Inventor： Yu-Chung LIEN ,  Zhenming ZHOU ,  Tomer Tzvi ELIASH

    IPC: G11C16/34 ,  G11C16/10 ,  G11C16/24 ,  G11C16/32

    Abstract: Implementations described herein relate to detecting a memory write reliability risk without using a write verify operation. In some implementations, a memory device may perform a program operation that includes a single program pulse and that does not include a program verify operation immediately after the single program pulse. The memory device may set a flag value based on comparing a transition time and a transition time threshold. The transition time may be a time to transition from a first voltage to a second voltage during the program operation. The memory device may selectively perform a mitigation operation based on whether the flag value is set to a first value or a second value.

    POWER LOSS ERROR DETECTION USING PARTIAL BLOCK HANDLING
    16.
    发明公开
    POWER LOSS ERROR DETECTION USING PARTIAL BLOCK HANDLING 审中-公开

    公开(公告)号：US20240170090A1

    公开(公告)日：2024-05-23

    申请号：US18492252

    申请日：2023-10-23

    Applicant: Micron Technology, Inc.

    Inventor： Peng ZHANG ,  Lei LIN ,  Zhongguang XU ,  Li-Te CHANG ,  Zhengang CHEN ,  Murong LANG ,  Zhenming ZHOU

    IPC: G11C29/52 ,  G11C16/10 ,  G11C16/26

    CPC classification number: G11C29/52 ,  G11C16/102 ,  G11C16/26

    Abstract: In some implementations, a memory device may determine that a power loss has occurred. The memory device may determine a last written page (LWP) location associated with an LWP of a block of a memory of the memory device. The memory device may determine one of: a word line group (WLG) associated with the LWP location and at least one WLG-dependent offset associated with the WLG, or a partial block (PB) fill ratio associated with the LWP location and at least one PB-fill-ratio-dependent offset associated with the PB fill ratio. The memory device may perform a power loss error detection procedure based on one of the at least one WLG-dependent offset or the at least one PB-fill-ratio offset by applying the one of the at least one WLG-dependent offset or the at least one PB-fill-ratio offset to at least one read reference voltage.

    MEMORY DEVICE WITH FAST WRITE MODE TO MITIGATE POWER LOSS
    17.
    发明公开
    MEMORY DEVICE WITH FAST WRITE MODE TO MITIGATE POWER LOSS 审中-公开

    公开(公告)号：US20240046990A1

    公开(公告)日：2024-02-08

    申请号：US17817288

    申请日：2022-08-03

    Applicant: Micron Technology, Inc.

    Inventor： Yu-Chung LIEN ,  Juane LI ,  Sead ZILDZIC, JR. ,  Zhenming ZHOU

    IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34

    CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/3459

    Abstract: Implementations described herein relate to a memory device with a fast write mode to mitigate power loss. In some implementations, the memory device may detect a condition associated with power supplied to the memory device. The memory device may detect one or more pending write operations to be performed to cause data to be written to memory cells of the memory device. The memory device may switch from a first voltage pattern, previously used by the memory device to write data to one or more memory cells of the memory device, to a second voltage pattern based on detecting the condition and based on detecting the one or more pending write operations. The memory device may perform at least one write operation, of the one or more pending write operations, using the second voltage pattern.

    ADAPTIVE FREQUENCY CONTROL FOR HIGH-SPEED MEMORY DEVICES
    19.
    发明申请
    ADAPTIVE FREQUENCY CONTROL FOR HIGH-SPEED MEMORY DEVICES 有权

    公开(公告)号：US20220058070A1

    公开(公告)日：2022-02-24

    申请号：US16996267

    申请日：2020-08-18

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Jian HUANG ,  Zhenming ZHOU ,  Zhongguang Xu ,  Murong Lang

    IPC: G06F11/07 ,  G06F11/10 ,  G11C16/26

    Abstract: A command to read specific data stored at a memory die is received. A read operation is performed while operating both a memory controller and the memory die simultaneously at a first frequency. A processor determines whether a first error rate associated with the memory die satisfies a first error threshold criterion (e.g., UECC). Responsive to determining that the first error rate satisfies the first error threshold criterion, the read operation is repeated while operating at least one of the memory controller or the memory die at a second frequency that is different from the first frequency. The processor determines whether a second error rate associated with the memory die satisfies a second error threshold criterion. Responsive to determining that the second error rate satisfies the second error threshold criterion (e.g. UECC persists), determining that the read operation has failed.

    DYNAMIC VOLTAGE SETTING OPTIMIZATION DURING LIFETIME OF A MEMORY DEVICE
    20.
    发明申请
    DYNAMIC VOLTAGE SETTING OPTIMIZATION DURING LIFETIME OF A MEMORY DEVICE 有权

    公开(公告)号：US20220012121A1

    公开(公告)日：2022-01-13

    申请号：US16925215

    申请日：2020-07-09

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Zhongguang XU ,  Murong LANG ,  Zhenming ZHOU

    IPC: G06F11/10 ,  G11C29/00 ,  G11C16/10

    Abstract: An initial level of sensing voltage is set based on one or more characteristics of the segment of the memory device. A count for operational cycles for a segment of a memory device is set. Responsive to determining that a number of operational cycles performed on the segment of the memory device has reached the set count of operational cycles, the sensing voltage is varied with respect to the initial level of sensing voltage. The sensing voltage is adjusted to a new level based on wearing of the segment of the memory device during the number of operational cycles performed on the segment of the memory device.

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