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    Metadata storage associated with wear-level operation requests
    11.
    发明授权
    Metadata storage associated with wear-level operation requests 有权
    与磨损级操作请求相关联的元数据存储

    公开(公告)号：US09152559B2

    公开(公告)日：2015-10-06

    申请号：US14536333

    申请日：2014-11-07

    Applicant: Micron Technology, Inc.

    Inventor： Procolo Carannante ,  Angelo Di Sena ,  Fabio Salvati ,  Giuseppe Ferrari ,  Anna Sorgente

    IPC: G06F12/00 ,  G06F12/02

    CPC classification number: G06F12/0246 ,  G06F2212/7207 ,  G06F2212/7211 ,  Y02D10/13

    Abstract: A method includes responding to a wear-level operation request by copying data from a first portion of a first memory array to a second portion of the first memory array, and copying metadata associated with the data from a third portion of a second memory array to a fourth portion of the second memory array. The first memory array includes a NAND or NAND-based memory array, and the second memory array includes non-volatile memory including at least one of the group consisting of: phase-change memory, EEPROM, and NOR flash memory.

    Abstract translation: 一种方法包括通过将数据从第一存储器阵列的第一部分复制到第一存储器阵列的第二部分来应对磨损级操作请求，以及将与数据相关联的数据从第二存储器阵列的第三部分复制到 第二存储器阵列的第四部分。 第一存储器阵列包括NAND或基于NAND的存储器阵列，并且第二存储器阵列包括非易失性存储器，其包括由以下组成的组中的至少一个：相变存储器，EEPROM和NOR闪存。

    DATA CACHING FOR FAST SYSTEM BOOT-UP
    14.
    发明公开
    DATA CACHING FOR FAST SYSTEM BOOT-UP 审中-公开

    公开(公告)号：US20240303087A1

    公开(公告)日：2024-09-12

    申请号：US18609981

    申请日：2024-03-19

    Applicant: Micron Technology, Inc.

    Inventor： Francesco Basso ,  Giuseppe Ferrari ,  Francesco Falanga ,  Massimo Iaculo

    IPC: G06F9/4401 ,  G06F12/0871

    CPC classification number: G06F9/4406 ,  G06F12/0871

    Abstract: Methods, systems, and devices for data caching for fast system boot-up are described. A memory system may create a linked mapping of addresses, which may also be referred to as a mixed page pointer table. The linked mapping may include logical addresses associated with commands received during a boot-up procedure, and their associated physical addresses. The linked mapping may also include a counter associated with each logical address to track how often the logical address is referenced during successive boot-up procedures. Over successive boot-up procedures, addresses may be added or removed from the linked mapping, and sequential addresses may be compressed. The memory device may use the linked mapping to predict which data may be accessed during the boot-up procedure, and may pre-transfer the data to volatile memory based on the prediction.

    Direct logical-to-physical address mapping for sequential physical addresses
    15.
    发明授权
    Direct logical-to-physical address mapping for sequential physical addresses 有权

    公开(公告)号：US12073113B2

    公开(公告)日：2024-08-27

    申请号：US17461469

    申请日：2021-08-30

    Applicant: Micron Technology, Inc.

    Inventor： Lalla Fatima Drissi ,  Doriana Tardio ,  Giuseppe D'Eliseo ,  Giuseppe Ferrari

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

    Abstract: Methods, systems, and devices for memory operations are described. A memory system may write data to sequential physical addresses of the memory system based on receiving multiple write commands, where the sequential physical addresses may be associated with sequential logical addresses. Based on writing the data, the memory system may receive a read command for data stored in the memory system, where the read command may include a logical address. The memory system may determine a physical address of the memory system where the data is stored based on the received logical address, a last logical address written at the memory system, and a sequence number group associated with the last logical address. Based on determining the physical address, the memory system may read the data stored at the physical address.

    AUTHENTICATED READING OF MEMORY SYSTEM DATA
    16.
    发明申请
    AUTHENTICATED READING OF MEMORY SYSTEM DATA 有权

    公开(公告)号：US20230126605A1

    公开(公告)日：2023-04-27

    申请号：US17664354

    申请日：2022-05-20

    Applicant: Micron Technology, Inc.

    Inventor： Lance W. Dover ,  Giuseppe Vito Portacci ,  Giuseppe Ferrari

    IPC: G06F12/14 ,  G06F21/79

    Abstract: Methods, systems, and devices for authenticated reading of memory system data are described. In some examples, a host system and a memory system may exchange keys used to grant the host system access to one or more protected regions of the memory system. The keys may be symmetric or asymmetric. In some cases, the host system may transmit a read command to access data stored at a protected region of the memory system, along with a signature generated using the key associated with the protected region. The memory system may verify the signature to determine whether the host is authorized to access the protected region, and may transmit the requested data to the host system. In some examples, the memory system may sign the returned data, so that the host system may verify the source of the data.

    SCHEME TO IMPROVE EFFICIENCY OF DEVICE GARBAGE COLLECTION IN MEMORY DEVICES
    17.
    发明申请
    SCHEME TO IMPROVE EFFICIENCY OF DEVICE GARBAGE COLLECTION IN MEMORY DEVICES 有权

    公开(公告)号：US20220414003A1

    公开(公告)日：2022-12-29

    申请号：US17902384

    申请日：2022-09-02

    Applicant: Micron Technology, Inc.

    Inventor： Xinghui Duan ,  Giuseppe D'Eliseo ,  Lalla Fatima Drissi ,  Giuseppe Ferrari ,  Eric Kwok Fung Yuen ,  Massimo Iaculo

    IPC: G06F12/02 ,  G06F12/1009

    Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus in which storage in the memory device is managed. An allocation can include conducting a garbage collection procedure to free up one or more blocks. In various embodiments, execution of a garbage collection procedure can be based on operation of two tables with respect to a logical to physical mapping table split into logical to physical mapping table regions saved in the memory device. The first table can maintain counts of valid pages in blocks for a logical to physical mapping table region. The second table can include bits to identify logical to physical mapping table regions involved in the garbage collection procedure based on the entries in the first table. Search of the second table can determine logical to physical mapping table regions involved in the garbage collection. Additional apparatus, systems, and methods are disclosed.

    Synchronizing NAND logical-to-physical table region tracking
    18.
    发明授权
    Synchronizing NAND logical-to-physical table region tracking 有权

    公开(公告)号：US11341041B2

    公开(公告)日：2022-05-24

    申请号：US16940015

    申请日：2020-07-27

    Applicant: Micron Technology, Inc.

    Inventor： Zhao Cui ,  Eric Kwok Fung Yuen ,  Guan Zhong Wang ,  Xinghui Duan ,  Giuseppe D'Eliseo ,  Giuseppe Ferrari

    IPC: G06F12/02 ,  G06F12/0873

    Abstract: Devices and techniques for synchronizing NAND logical-to-physical table region tracking are described herein. Table region data structures for physical blocks are maintained. These structures include logical-to-physical (L2P) mapping table portions that point to the respective physical blocks. When garbage collection is performed on a block, table region structures for that block, and another (e.g., the next block to be garbage collected) are read to avoid loading L2P table regions that do not point to the block. If any of the read portions of the L2P table region fail to point to either the block or the other block, these L2P table portions are removed from the loaded table region data structures.

    Reading sequential data from memory using a pivot table
    19.
    发明授权
    Reading sequential data from memory using a pivot table 有权

    公开(公告)号：US11151052B2

    公开(公告)日：2021-10-19

    申请号：US16713552

    申请日：2019-12-13

    Applicant: Micron Technology, Inc.

    Inventor： Giuseppe D'Eliseo ,  Carminantonio Manganelli ,  Paolo Papa ,  Yoav Weinberg ,  Giuseppe Ferrari ,  Massimo Laculo ,  Lalla Fatima Drissi

    IPC: G06F12/1009

    Abstract: In one approach, a computer storage device has one or more pivot tables and corresponding bit maps stored in volatile memory. The storage device has non-volatile storage media that stores data for a host device. The pivot tables and bit maps are used to determine physical addresses of the non-volatile storage media for logical addresses received in commands from the host device that are determined to be within a sequential address range (e.g., LBAs that are part of a prior sequential write operation by the host device). When a command is received by the storage device that includes a logical address within the sequential address range, then one of the pivot tables and its corresponding bit map are used to determine the physical address of the non-volatile storage media that corresponds to the logical address.

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