公开(公告)号：US20160064237A1

公开(公告)日：2016-03-03

申请号：US14473220

申请日：2014-08-29

Applicant: MACRONIX International Co., Ltd.

Inventor： Chin-Cheng Yang

IPC: H01L21/308

CPC classification number: H01L21/3086 ,  G03F7/26 ,  H01L21/0337 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/32139

Abstract: A method of forming a semiconductor device is disclosed. A substrate having a first area and a second area is provided. A target layer and a hard mask layer are sequentially formed on the substrate in the first area and in the second area. Transfer patterns are formed in a spacer form on the hard mask layer in the first area. A photoresist layer is formed directly on the hard mask layer, and covers the transfer patterns and the hard mask layer in the first area and in the second area. The photoresist layer in the first area is removed. The hard mask layer is patterned by using the transfer patterns as a mask.

Abstract translation: 公开了一种形成半导体器件的方法。 提供具有第一区域和第二区域的衬底。 在第一区域和第二区域中的基板上依次形成目标层和硬掩模层。 在第一区域的硬掩模层上以间隔物的形式形成转印图案。 光致抗蚀剂层直接形成在硬掩模层上，并且覆盖第一区域和第二区域中的转印图案和硬掩模层。 去除第一区域中的光致抗蚀剂层。 通过使用转印图案作为掩模来对硬掩模层进行图案化。

公开(公告)号：US20160062227A1

公开(公告)日：2016-03-03

申请号：US14475781

申请日：2014-09-03

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chin-Cheng Yang

IPC: G03F1/42 ,  G01B21/00

CPC classification number: G03F1/76 ,  G03F1/78 ,  G03F1/84

Abstract: A method of monitoring mask uniformity includes selecting a unit monitor mark pattern and monitor mark locations based on a main cell size, determining a unit monitor mark sampling location and measurement methodology, and starting a mask making process. The mask critical dimension uniformity (CDU) is measured and data is analyzed. A process impact factor is identified if the mask CDU is not within a predetermined specification, and a mask making process parameter is adjusted based on the identified process impact factor. The mask making process, measuring, identifying and adjusting steps are repeated until the mask CDU is within the predetermined specification.

Abstract translation: 监视掩模均匀性的方法包括基于主单元尺寸选择单位监视标记图案和监视标记位置，确定单位监视标记采样位置和测量方法，以及开始掩模制作过程。 测量掩模临界尺寸均匀度（CDU）并分析数据。 如果掩模CDU不在预定的规范内，则识别过程影响因子，并且基于所识别的过程影响因子调整掩模制作工艺参数。 重复掩模制作过程，测量，识别和调整步骤，直到掩模CDU在预定规格内。

公开(公告)号：US20230309299A1

公开(公告)日：2023-09-28

申请号：US17702559

申请日：2022-03-23

Applicant: MACRONIX International Co., Ltd.

Inventor： Chin-Cheng Yang

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11519 ,  H01L27/11565

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157

Abstract: A memory device includes a dielectric substrate, an interlayer structure, a plurality of channel pillars, a plurality of charge storage structures, a plurality of slit structures and an assistance structure. The dielectric substrate includes an array region and an iso region aside the array region. The interlayer structure is disposed in the array region and the iso region. The channel pillars penetrate through the interlayer structure in the array region. The charge storage structures are disposed between the interlayer structure and the plurality of channel pillars. The slit structures are disposed between the plurality of channel pillars, penetrate through the interlayer structure in the array region, and divide the interlayer structure into a plurality of blocks. The assistance structure is arranged in the iso region. The assistance structure includes at least one dummy slit structure having an extension direction different from an extension direction of the plurality of slit structures.

公开(公告)号：US20230061128A1

公开(公告)日：2023-03-02

申请号：US17464479

申请日：2021-09-01

Applicant: MACRONIX International Co., Ltd.

Inventor： Chin-Cheng Yang

IPC: H01L23/60 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/768

Abstract: A memory device includes a substrate, a metal interconnect structure, a first stack structure, a second stack structure, a first conductive pillar, and a first contact. The metal interconnect structure is located on the substrate. The first stack structure is located on the metal interconnect structure and includes first conductive layers and first insulating layer that alternate with each other, and an insulating structure embedded in the first conductive layers and the first insulating layers. The second stack structure is located on the first stack structure and includes second insulating layers and middle layers that alternate with each other. The first conductive pillar is embedded in the insulating structure to be electrically connected to the metal interconnect structure. The first contact passes through the second insulating layers and the middle layers of the second stack structure to be electrically connected to the first conductive pillar.

公开(公告)号：US20200335509A1

公开(公告)日：2020-10-22

申请号：US16391130

申请日：2019-04-22

Applicant: MACRONIX International Co., Ltd.

Inventor： Chin-Cheng Yang

IPC: H01L27/115 ,  H01L23/544

Abstract: Reference marks for forming a staircase structure are disposed along slit areas of a 3D memory structure, and slits of the 3D memory structure are formed on the slit areas. In a staircase area, the reference marks are formed by etching the topmost one of stacked layers, having a pair of a dielectric layer and a sacrificial layer, in a stacked structure.

公开(公告)号：US10580789B2

公开(公告)日：2020-03-03

申请号：US15645824

申请日：2017-07-10

Applicant: MACRONIX International Co., Ltd.

Inventor： Chi-Hao Huang ,  Chin-Cheng Yang

IPC: H01L27/11578 ,  H01L27/11582 ,  H01L27/11573 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/265 ,  H01L21/762 ,  H01L21/266 ,  H01L21/306 ,  H01L27/108

Abstract: A semiconductor device and method of fabricating the same are provided. The semiconductor device includes a substrate having a trench and an etching stop layer. The etching stop layer is disposed in the substrate and surrounds the bottom surface and a portion of a sidewall of the trench.

公开(公告)号：US10474027B2

公开(公告)日：2019-11-12

申请号：US15810551

申请日：2017-11-13

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chin-Cheng Yang

IPC: G03F1/42 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11526 ,  H01L27/11568 ,  H01L27/11582 ,  G03F1/76 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  G03F1/80 ,  H01L27/11573 ,  G03F9/00 ,  H01L27/11548 ,  H01L27/11575

Abstract: A method for forming an aligned mask comprises etching a reference mark on a substrate to demarcate a boundary of an etch region; forming an etch mask on the substrate, using an exposure setting, the etch mask having a boundary; and measuring a distance between the reference mark and the boundary. When the measured distance is outside a margin of a target distance, then the etch mask is removed from the substrate, the exposure setting is changed, a next etch mask is formed using the changed exposure setting, and said measuring is repeated. A set of reference marks can be etched on a top level in a set of levels to demarcate boundaries of etch regions. An etch-trim process can be performed to form steps in the set of levels, wherein the etch-trim process includes at least first and second etch-trim cycles using first and second reference marks.

公开(公告)号：US09425209B1

公开(公告)日：2016-08-23

申请号：US14846262

申请日：2015-09-04

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chin-Cheng Yang ,  Lo-Yuen Lin ,  Yu-Wei Jiang

IPC: H01L29/76 ,  H01L27/115 ,  H01L29/788 ,  H01L23/528 ,  H01L29/792

CPC classification number: H01L27/11582 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575

Abstract: An integrated circuit includes blocks and global lines overlying the blocks. The blocks include a plurality of levels including two dimensional arrays of memory cells having horizontal lines and being intersected by vertical lines coupled to corresponding memory cells. Levels include contact pads communicating with horizontal lines for a given block. The global lines include connectors. Connectors coupled to given global lines are coupled to landing areas on corresponding contact pads of the blocks. The blocks include first and second blocks disposed so that a first set of the contact pads associated with the first block are next to a second set of contact pads associated with the second block. The landing areas of the contact pads of the first and second blocks are mirror image surfaces of one another. The horizontal lines can be bit lines and the vertical lines can be word lines.

Abstract translation: 集成电路包括覆盖块的块和全局线。 这些块包括多个级，包括具有水平线的存储器单元的二维阵列，并且与由相应的存储器单元耦合的垂直线相交。 电平包括与给定块的水平线通信的接触焊盘。 全球线路包括连接器。 耦合到给定的全局线的连接器耦合到块的相应接触焊盘上的着陆区域。 这些块包括第一和第二块，其被布置成使得与第一块相关联的第一组接触垫相邻于与第二块相关联的第二组接触垫。 第一和第二块的接触垫的着陆区域是彼此的镜像表面。 水平线可以是位线，垂直线可以是字线。

公开(公告)号：US09269660B2

公开(公告)日：2016-02-23

申请号：US13772121

申请日：2013-02-20

Applicant: Macronix International Co., Ltd.

Inventor： Shih-Hung Chen ,  Hang-Ting Lue ,  Hong-Ji Lee ,  Chin-Cheng Yang

IPC: H01L23/50 ,  H01L23/522 ,  H01L23/48 ,  H01L27/112 ,  H01L21/768 ,  H01L27/02 ,  H01L27/115 ,  H01L23/00 ,  H01L27/06

CPC classification number: H01L23/50 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76838 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5226 ,  H01L24/19 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/11206 ,  H01L27/11286 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/00

Abstract: A three-dimensional stacked IC device includes a stack of at least first, second, third and fourth contact levels at an interconnect region. Each contact level has a conductive layer and an insulation layer. First, second, third and fourth electrical conductors pass through portions of the stack of contact levels. The first, second, third and fourth electrical conductors are in electrical contact with the first, second, third and fourth conductive layers, respectively. A dielectric sidewall spacer circumferentially surrounds the second, third and fourth electrical conductors so that the second, third and fourth electrical conductors only electrically contact the respective second, third and fourth conductive layers.

Abstract translation: 三维堆叠IC器件包括在互连区域处的至少第一，第二，第三和第四接触电平的堆叠。 每个接触层具有导电层和绝缘层。 第一，第二，第三和第四电导体穿过接触层叠层的部分。 第一，第二，第三和第四电导体分别与第一，第二，第三和第四导电层电接触。 电介质侧壁间隔件周向地围绕第二，第三和第四电导体，使得第二，第三和第四电导体仅电相接触相应的第二，第三和第四导电层。

公开(公告)号：US09147692B2

公开(公告)日：2015-09-29

申请号：US14143767

申请日：2013-12-30

Applicant: MACRONIX International Co., Ltd.

Inventor： Chin-Cheng Yang

IPC: H01L21/4763 ,  H01L27/115 ,  H01L21/768 ,  G11C5/06 ,  H01L27/02

CPC classification number: H01L27/11565 ,  G11C5/063 ,  H01L21/76895 ,  H01L27/0207 ,  H01L27/11568 ,  H01L27/11575

Abstract: A method for forming separate narrow lines is described. A target layer is formed over a substrate. Base patterns are formed over the target layer. Target line patterns and connection patterns between the ends of the target line patterns are formed as spacers on the sidewalls of the base patterns. The base patterns are removed. The target line patterns and the connection patterns are transferred to the target layer to form target lines and connection segments between the ends of the target lines. At least a portion of each connection segment is removed to disconnect the target lines while other area of the substrate is subjected to a patterned removal treatment.

Abstract translation: 描述形成分开的窄线的方法。 目标层形成在衬底上。 在目标层上形成基本图案。 目标线图案和目标线图案的端部之间的连接图案在基底图案的侧壁上形成为间隔物。 基本图案被删除。 目标线图案和连接图案被传送到目标层以在目标线的端部之间形成目标线和连接段。 每个连接段的至少一部分被去除以断开目标线，而衬底的其它区域经受图案化去除处理。