公开(公告)号：US6111454A

公开(公告)日：2000-08-29

申请号：US281937

申请日：1999-03-31

申请人： Takashi Shinohe ,  Masakazu Yamaguchi ,  Kimihiro Hoshi

发明人： Takashi Shinohe ,  Masakazu Yamaguchi ,  Kimihiro Hoshi

IPC分类号： H03K17/042 ,  H03K17/687 ,  H03K17/785

CPC分类号： H03K17/785 ,  H03K17/04206

摘要： A semiconductor device comprises a voltage-driven switching element having a cathode and an anode, in which a voltage is to be applied between the cathode and anode, a power-supply circuit connected between the cathode and anode of the voltage-driven switching element and comprising capacitors, resistors and a reverse current-low preventing diode, for generating an intermediate voltage, a charging switching element for charging a gate of the voltage-driven switching element, using the intermediate voltage generated by the power-supply circuit, a discharging switching element for discharging the gate of the voltage-driven switching element, and a photovoltaic element for generating a photovoltaic power to control to drive the charging switching element and the discharging switching element.

摘要翻译： 半导体器件包括具有阴极和阳极的电压驱动开关元件，其中在阴极和阳极之间施加电压，连接在电压驱动的开关元件的阴极和阳极之间的电源电路和 包括用于产生中间电压的电容器，电阻器和反向电流低阻抗二极管，使用由电源电路产生的中间电压对电压驱动的开关元件的栅极进行充电的充电开关元件，放电开关 用于对电压驱动的开关元件的栅极进行放电的元件，以及用于产生光伏功率以控制驱动充电开关元件和放电开关元件的光电元件。

公开(公告)号：US6054748A

公开(公告)日：2000-04-25

申请号：US41799

申请日：1998-03-13

申请人： Masanori Tsukuda ,  Takashi Shinohe ,  Masakazu Yamaguchi

发明人： Masanori Tsukuda ,  Takashi Shinohe ,  Masakazu Yamaguchi

IPC分类号： H01L21/329 ,  H01L21/331 ,  H01L29/06 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78 ,  H01L29/861 ,  H01L23/58

CPC分类号： H01L29/861 ,  H01L29/0615 ,  H01L29/1095 ,  H01L29/66136 ,  H01L29/66333 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/0657 ,  H01L2924/0002

摘要： A semiconductor power device includes a high-resistance semiconductor substrate of the first conductivity type having first and second major surfaces and a recess in either one of the first and second major surfaces, and a semiconductor power element with a field relaxation structure, at least part of which is formed in a region of the semiconductor substrate where the recess is formed.

摘要翻译： 半导体功率器件包括具有第一和第二主表面的第一导电类型的高电阻半导体衬底和在第一和第二主表面中的任一个中的凹部，以及具有场弛豫结构的半导体功率元件，至少部分 其形成在形成有凹部的半导体基板的区域中。

公开(公告)号：US09029869B2

公开(公告)日：2015-05-12

申请号：US13034264

申请日：2011-02-24

申请人： Hiroshi Kono ,  Takashi Shinohe ,  Chiharu Ota ,  Makoto Mizukami ,  Takuma Suzuki ,  Johji Nishio

发明人： Hiroshi Kono ,  Takashi Shinohe ,  Chiharu Ota ,  Makoto Mizukami ,  Takuma Suzuki ,  Johji Nishio

IPC分类号： H01L29/15 ,  H01L29/739 ,  H01L29/10 ,  H01L29/66

CPC分类号： H01L29/7395 ,  H01L29/1033 ,  H01L29/66333

摘要： One embodiment of a semiconductor device includes: a silicon carbide substrate including first and second principal surfaces; a first-conductive-type silicon carbide layer on the first principal surface; a second-conductive-type first silicon carbide region at a surface of the first silicon carbide layer; a first-conductive-type second silicon carbide region at the surface of the first silicon carbide region; a second-conductive-type third silicon carbide region at the surface of the first silicon carbide region; a second-conductive-type fourth silicon carbide region formed between the first silicon carbide region and the second silicon carbide region, and having an impurity concentration higher than that of the first silicon carbide region; a gate insulator; a gate electrode formed on the gate insulator; an inter-layer insulator; a first electrode connected to the second silicon carbide region and the third silicon carbide region; and a second electrode on the second principal surface.

摘要翻译： 半导体器件的一个实施例包括：包含第一和第二主表面的碳化硅衬底; 第一主表面上的第一导电型碳化硅层; 在所述第一碳化硅层的表面处的第二导电型第一碳化硅区域; 在第一碳化硅区域的表面处的第一导电型第二碳化硅区域; 在第一碳化硅区域的表面处的第二导电型第三碳化硅区域; 在第一碳化硅区域和第二碳化硅区域之间形成的杂质浓度高于第一碳化硅区域的第二导电型第四碳化硅区域; 栅极绝缘体; 形成在栅极绝缘体上的栅电极; 层间绝缘体; 连接到所述第二碳化硅区域和所述第三碳化硅区域的第一电极; 和在第二主表面上的第二电极。

公开(公告)号：US08569795B2

公开(公告)日：2013-10-29

申请号：US13217472

申请日：2011-08-25

申请人： Hiroshi Kono ,  Yukio Nakabayashi ,  Takashi Shinohe ,  Makoto Mizukami

发明人： Hiroshi Kono ,  Yukio Nakabayashi ,  Takashi Shinohe ,  Makoto Mizukami

IPC分类号： H01L33/32 ,  H01L29/80 ,  H01L29/16 ,  H01L27/11 ,  H01L27/10

CPC分类号： H01L29/7802 ,  H01L21/049 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/4966 ,  H01L29/66068 ,  H01L29/7813

摘要： A semiconductor device of an embodiment includes: a silicon carbide substrate including first and second principal surfaces; a first conductive-type first silicon carbide layer provided on the first principal surface of the silicon carbide substrate; a second conductive-type first silicon carbide region formed on a surface of the first silicon carbide layer; a first conductive-type second silicon carbide region formed on a surface of the first silicon carbide region; a second conductive-type third silicon carbide region formed on the surface of the first silicon carbide region; a gate insulating film continuously formed on the surfaces of the first silicon carbide layer, the first silicon carbide region, and the second silicon carbide region; a first electrode formed of silicon carbide formed on the gate insulating film; a second electrode formed on the first electrode; an interlayer insulating film for covering the first and second electrodes; a third electrode electrically connected to the second silicon carbide region and the third silicon carbide region; and a fourth electrode formed on the second principal surface of the silicon carbide substrate.

摘要翻译： 实施例的半导体器件包括：碳化硅衬底，其包括第一和第二主表面; 设置在碳化硅衬底的第一主表面上的第一导电型第一碳化硅层; 形成在所述第一碳化硅层的表面上的第二导电型第一碳化硅区; 形成在所述第一碳化硅区域的表面上的第一导电型第二碳化硅区域; 形成在所述第一碳化硅区域的表面上的第二导电型第三碳化硅区域; 连续形成在所述第一碳化硅层，所述第一碳化硅区域和所述第二碳化硅区域的表面上的栅极绝缘膜; 形成在所述栅极绝缘膜上的由碳化硅形成的第一电极; 形成在第一电极上的第二电极; 用于覆盖第一和第二电极的层间绝缘膜; 电连接到第二碳化硅区域和第三碳化硅区域的第三电极; 以及形成在碳化硅衬底的第二主表面上的第四电极。

公开(公告)号：US20130137253A1

公开(公告)日：2013-05-30

申请号：US13705610

申请日：2012-12-05

申请人： Hiroshi KONO ,  Takashi Shinohe

发明人： Hiroshi KONO ,  Takashi Shinohe

IPC分类号： H01L21/04

CPC分类号： H01L21/04 ,  H01L29/0619 ,  H01L29/0834 ,  H01L29/0839 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/7802

摘要： A semiconductor device includes: a silicon carbide substrate having first and second main surfaces; a first silicon carbide layer provided on the first main surface of the silicon carbide substrate; first silicon carbide regions formed on a surface of the first silicon carbide layer; second and third silicon carbide regions formed on respective surfaces of the first silicon carbide regions; a fourth silicon carbide region formed between facing first silicon carbide regions with the first silicon carbide layer therebetween; a gate insulating film formed continuously on surfaces of the first silicon carbide regions, the first silicon carbide layer, and the fourth silicon carbide region; a gate electrode formed on the gate insulating film; an interlayer insulating film covering the gate electrode; a first electrode electrically connected to the second and third silicon carbide regions; and a second electrode formed on the second main surface of the silicon carbide substrate.

摘要翻译： 半导体器件包括：具有第一和第二主表面的碳化硅衬底; 设置在所述碳化硅衬底的所述第一主表面上的第一碳化硅层; 第一碳化硅区域形成在第一碳化硅层的表面上; 形成在第一碳化硅区域的相应表面上的第二和第三碳化硅区域; 形成在面对的第一碳化硅区域之间的第四碳化硅区域，其间具有第一碳化硅层; 在第一碳化硅区域，第一碳化硅层和第四碳化硅区域的表面上连续形成的栅极绝缘膜; 形成在栅极绝缘膜上的栅电极; 覆盖栅电极的层间绝缘膜; 电连接到第二和第三碳化硅区域的第一电极; 以及形成在碳化硅衬底的第二主表面上的第二电极。

公开(公告)号：US20120199846A1

公开(公告)日：2012-08-09

申请号：US13216413

申请日：2011-08-24

申请人： Tatsuo SHIMIZU ,  Takashi Shinohe

发明人： Tatsuo SHIMIZU ,  Takashi Shinohe

IPC分类号： H01L29/16 ,  H01L21/20

CPC分类号： H01L29/7802 ,  H01L21/044 ,  H01L21/0465 ,  H01L29/1608 ,  H01L29/517 ,  H01L29/66068 ,  H01L29/7395

摘要： A semiconductor device of an embodiment at least includes: a SiC substrate; and a gate insulating film formed on the SiC substrate, wherein at an interface between the SiC substrate and the gate insulating film, some of elements of both of or one of Si and C in an outermost surface of the SiC substrate are replaced with at least one type of element selected from nitrogen, phosphorus, and arsenic.

摘要翻译： 实施例的半导体器件至少包括：SiC衬底; 以及形成在所述SiC衬底上的栅极绝缘膜，其中在所述SiC衬底和所述栅极绝缘膜之间的界面处，至少在所述SiC衬底的最外表面中的Si和C中的一个或其中的一个元素被替换 一种选自氮，磷和砷的元素。

公开(公告)号：US07947988B2

公开(公告)日：2011-05-24

申请号：US12199848

申请日：2008-08-28

申请人： Hiroshi Kono ,  Takashi Shinohe ,  Chiharu Ota ,  Johji Nishio

发明人： Hiroshi Kono ,  Takashi Shinohe ,  Chiharu Ota ,  Johji Nishio

IPC分类号： H01L29/15

CPC分类号： H01L29/7802 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7395

摘要： A semiconductor device includes an SiC substrate, a first SiC layer of first conductivity provided on the substrate, a second SiC layer of second conductivity provided on the first SiC layer, first and second SiC regions provided in the second SiC layer, facing each other and having the same depth, a third SiC region extending through the first SiC region and reaching the first SiC layer, a gate insulator formed on the first and second SiC regions and the second SiC layer interposed therebetween, a gate electrode formed on the gate insulator, a first contact of first conductivity formed on the second SiC region, a second contact of second conductivity formed on the second SiC region, reaching the second SiC layer through the second SiC region, and a top electrode formed on the first and second contacts, and a bottom electrode formed on a back surface of the substrate.

摘要翻译： 半导体器件包括SiC衬底，设置在衬底上的第一导电性第一SiC层，设置在第一SiC层上的第二导电性第二SiC层，设置在第二SiC层中的第一和第二SiC区域彼此面对， 具有相同深度的第三SiC区域延伸穿过第一SiC区域并到达第一SiC层，形成在第一和第二SiC区域上的第二SiC层和形成在栅极绝缘体上的第二SiC层的栅绝缘体， 形成在第二SiC区域上的第一导电体的第一接触，形成在第二SiC区域上的第二导电体的第二接触通过第二SiC区域到达第二SiC层，以及形成在第一和第二接触体上的顶部电极，以及 形成在基板的背面上的底部电极。

公开(公告)号：US20100308343A1

公开(公告)日：2010-12-09

申请号：US12846400

申请日：2010-07-29

申请人： Takuma Suzuki ,  Hiroshi Kono ,  Takashi Shinohe

发明人： Takuma Suzuki ,  Hiroshi Kono ,  Takashi Shinohe

IPC分类号： H01L29/78 ,  H01L29/24

CPC分类号： H01L29/7802 ,  H01L21/0465 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/7816

摘要： According to the embodiment, a semiconductor device includes an SiC substrate of a first or second conductivity type. An SiC layer of the first conductivity type is formed on a front surface of the substrate, a first SiC region of the second conductivity type is formed on the SiC layer, a second SiC region of the first conductivity type is formed within a surface of the first SiC region, a gate dielectric is continuously formed on the SiC layer, the second SiC region, and the surface of the first SiC region interposed between the SiC layer and the second SiC region, a gate electrode is formed on the gate dielectric, a first electrode is embedded in a trench selectively formed in a part where the first SiC region adjoins the second SiC region, and a second electrode is formed on a back surface of the substrate.

摘要翻译： 根据实施例，半导体器件包括第一或第二导电类型的SiC衬底。 第一导电类型的SiC层形成在基板的前表面上，第二导电类型的第一SiC区域形成在SiC层上，第一导电类型的第二SiC区域形成在 第一SiC区域，在SiC层，第二SiC区域和介于SiC层和第二SiC区域之间的第一SiC区域的表面上连续地形成栅极电介质，在栅极电介质上形成栅电极， 第一电极嵌入在第一SiC区域与第二SiC区域相邻的部分中选择性地形成的沟槽中，并且在衬底的背面上形成第二电极。

公开(公告)号：US07368783B2

公开(公告)日：2008-05-06

申请号：US11230492

申请日：2005-09-21

申请人： Makoto Mizukami ,  Takashi Shinohe

发明人： Makoto Mizukami ,  Takashi Shinohe

IPC分类号： H01L29/94

CPC分类号： H01L29/7813 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/66666 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7828 ,  H01L29/8083

摘要： A semiconductor device includes a semiconductor substrate of a first conductivity type, a lightly-doped semiconductor layer of the first conductivity type formed on the first major surface of the substrate, a first semiconductor region of the first conductivity type formed on an island-shaped region on the lightly-doped semiconductor layer, a first electrode surrounding the first semiconductor region and buried at a deeper position than the first semiconductor region, a second semiconductor region formed on the second major surface of the substrate, a buried field relaxation layer formed in the lightly-doped semiconductor layer between a bottom surface of the first electrode and the second semiconductor region, including a first field relaxation layer of the first conductivity type and second field relaxation layers of the second conductivity type formed at two ends of the first field relaxation layer, second and third electrodes formed on the first and second semiconductor regions, respectively.

摘要翻译： 半导体器件包括第一导电类型的半导体衬底，形成在衬底的第一主表面上的第一导电类型的轻掺杂半导体层，形成在岛状区域上的第一导电类型的第一半导体区域 在所述轻掺杂半导体层上，包围所述第一半导体区并且埋藏在比所述第一半导体区更深的位置的第一电极，形成在所述衬底的所述第二主表面上的第二半导体区， 在第一电极的底表面和第二半导体区域之间的轻掺杂半导体层，包括第一导电类型的第一场弛豫层和形成在第一场弛豫层两端的第二导电类型的第二场弛豫层 ，形成在第一和第二半导体区域上的第二和第三电极， 分别。

公开(公告)号：US20080001159A1

公开(公告)日：2008-01-03

申请号：US11821740

申请日：2007-06-25

申请人： Chiharu Ota ,  Johji Nishio ,  Tetsuo Hatakeyama ,  Takashi Shinohe

发明人： Chiharu Ota ,  Johji Nishio ,  Tetsuo Hatakeyama ,  Takashi Shinohe

IPC分类号： H01L29/04

CPC分类号： H01L29/66712 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/1608 ,  H01L29/402 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/66143 ,  H01L29/66333 ,  H01L29/7395 ,  H01L29/7811 ,  H01L29/8611 ,  H01L29/872

摘要： A semiconductor device includes a semiconductor substrate of a first conductivity type having a top surface and a bottom surface, a semiconductor layer of a first conductivity type formed on the top surface of the semiconductor substrate, and having an active region and an edge termination region surrounding the active region, a first semiconductor region of a second conductivity type formed in the edge termination region adjacent to an edge of the active region, a second semiconductor region of a second conductivity type buried in the edge termination region in a sheet shape or a mesh shape substantially in parallel with a surface of the semiconductor layer, a first electrode formed on the active region of the semiconductor layer and a part of the first semiconductor region, and a second electrode formed on the bottom surface of the semiconductor substrate.

摘要翻译： 半导体器件包括具有顶表面和底表面的第一导电类型的半导体衬底，形成在半导体衬底的顶表面上的第一导电类型的半导体层，并且具有活动区域和围绕 有源区域，形成在与有源区域的边缘相邻的边缘终端区域中的第二导电类型的第一半导体区域，第二导电类型的第二半导体区域以片状或网状掩埋在边缘终端区域中 形状基本上与半导体层的表面平行，形成在半导体层的有源区和第一半导体区的一部分上的第一电极和形成在半导体衬底的底表面上的第二电极。