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    Self-passivation of copper damascene
    13.
    发明授权
    Self-passivation of copper damascene 失效
    铜大马士革自钝化

    公开(公告)号：US6083835A

    公开(公告)日：2000-07-04

    申请号：US121707

    申请日：1998-07-24

    申请人： Shau-Lin Shue ,  Chen-Hua Yu

    发明人： Shau-Lin Shue ,  Chen-Hua Yu

    IPC分类号： H01L21/768 ,  H01L21/44

    CPC分类号： H01L21/76856 ,  H01L21/7684 ,  H01L21/76849

    摘要： A process for forming damascene wiring within an integrated circuit is described. After the trenches have been filled and planarized, normal dishing of the copper is present. This is then eliminated by depositing a layer of a chrome-copper alloy over the damascene wiring and then planarizing this layer so that it covers only the copper in the damascene trench. Then, while the IMD is deposited, some of the chromium in the alloy gets selectively oxidized, resulting in a self-aligned barrier layer of chromium oxide at the copper to IMD interface.

    摘要翻译： 描述了在集成电路内形成镶嵌线的工艺。 在沟槽被填充和平坦化之后，存在铜的正常凹陷。 然后通过在大马士革布线上沉积一层铬铜合金，然后平坦化该层，使其仅覆盖大马士革沟槽中的铜而消除。 然后，当沉积IMD时，合金中的一些铬被选择性地氧化，导致在铜到IMD界面处的氧化铬的自对准势垒层。

    Copper interconnect structure and method for forming the same
    14.
    发明授权
    Copper interconnect structure and method for forming the same 有权
    铜互连结构及其形成方法

    公开(公告)号：US08941239B2

    公开(公告)日：2015-01-27

    申请号：US13586676

    申请日：2012-08-15

    申请人： Chen-Hua Yu ,  Shau-Lin Shue ,  Hsiang-Huan Lee ,  Ching-Fu Yeh

    发明人： Chen-Hua Yu ,  Shau-Lin Shue ,  Hsiang-Huan Lee ,  Ching-Fu Yeh

    IPC分类号： H01L23/48 ,  H01L21/14

    CPC分类号： H01L21/76871 ,  H01L21/76846 ,  H01L2221/1089

    摘要： A copper interconnect structure in a semiconductor device including an opening formed in a dielectric layer of the semiconductor device, the opening having sidewalls and a bottom. A first barrier layer is conformally deposited on the sidewalls and the bottom of the opening. A first seed layer is conformally deposited on the first barrier layer. A second barrier layer is conformally deposited on the first seed layer. A second seed layer is conformally deposited on the second barrier layer and a conductive plug is deposited in the opening of the dielectric layer.

    摘要翻译： 一种半导体器件中的铜互连结构，包括形成在半导体器件的电介质层中的开口，该开口具有侧壁和底部。 第一阻挡层保形地沉积在开口的侧壁和底部上。 第一种子层共形沉积在第一阻挡层上。 第二阻挡层被共形沉积在第一籽晶层上。 第二种子层被共形沉积在第二阻挡层上，并且导电塞被沉积在电介质层的开口中。

    Low resistance high reliability contact via and metal line structure for semiconductor device
    16.
    发明授权
    Low resistance high reliability contact via and metal line structure for semiconductor device 有权
    低电阻高可靠性接触通孔和半导体器件的金属线结构

    公开(公告)号：US08106512B2

    公开(公告)日：2012-01-31

    申请号：US12845852

    申请日：2010-07-29

    申请人： Hsiang-Huan Lee ,  Ming Han Lee ,  Ming-Shih Yeh ,  Chen-Hua Yu ,  Shau-Lin Shue

    发明人： Hsiang-Huan Lee ,  Ming Han Lee ,  Ming-Shih Yeh ,  Chen-Hua Yu ,  Shau-Lin Shue

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L23/53238 ,  H01L21/28562 ,  H01L21/76846 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76883 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The structures and methods described above provide mechanisms to improve interconnect reliability and resistivity. The interconnect reliability and resistivity are improved by using a composite barrier layer, which provides good step coverage, good copper diffusion barrier, and good adhesion with adjacent layers. The composite barrier layer includes an ALD barrier layer to provide good step coverage. The composite barrier layer also includes a barrier-adhesion-enhancing film, which contains at least an element or compound that contains Mn, Cr, V, Ti, or Nb to improve adhesion. The composite barrier layer may also include a Ta or Ti layer between the ALD barrier layer and the barrier-adhesion-enhancing layer.

    摘要翻译： 上述结构和方法提供了提高互连可靠性和电阻率的机制。 通过使用复合阻挡层来提高互连的可靠性和电阻率，该复合阻挡层提供良好的台阶覆盖率，良好的铜扩散阻挡层和与相邻层的良好粘附性。 复合阻挡层包括ALD阻挡层以提供良好的阶梯覆盖。 复合阻挡层还包括至少包含含有Mn，Cr，V，Ti或Nb的元素或化合物以提高粘合性的阻隔增粘膜。 复合阻挡层还可以包括在ALD阻挡层和阻挡增粘层之间的Ta或Ti层。

    Dual damascene structure employing nitrogenated silicon carbide and non-nitrogenated silicon carbide etch stop layers
    18.
    发明授权
    Dual damascene structure employing nitrogenated silicon carbide and non-nitrogenated silicon carbide etch stop layers 有权
    采用氮化碳化硅和非氮化碳化硅蚀刻停止层的双镶嵌结构

    公开(公告)号：US06562725B2

    公开(公告)日：2003-05-13

    申请号：US09899420

    申请日：2001-07-05

    申请人： Ming-Hsing Tsai ,  Ching-Hua Hsieh ,  Shau-Lin Shue ,  Chen-Hua Yu

    发明人： Ming-Hsing Tsai ,  Ching-Hua Hsieh ,  Shau-Lin Shue ,  Chen-Hua Yu

    IPC分类号： H01L2100

    CPC分类号： H01L21/76829 ,  H01L21/31116 ,  H01L21/314 ,  H01L21/7681 ,  H01L21/76834

    摘要： Within a dual damascene method for forming a dual damascene aperture within a microelectronic fabrication there is employed a first etch stop layer formed of a first material and a second etch stop layer formed of a second material. One of the first material and the second material is a non-nitrogenated silicon carbide material and the other of the first material and the second material is a nitrogenated silicon carbide material. By employing the first material and the second material, there may be etched completely through the first etch stop layer to reach a contact region formed there beneath while not etching completely through the second etch stop layer to reach a first dielectric layer formed there beneath.

    摘要翻译： 在用于在微电子制造中形成双镶嵌孔的双镶嵌方法中，采用由第一材料形成的第一蚀刻停止层和由第二材料形成的第二蚀刻停止层。 第一材料和第二材料之一是非氮化碳化硅材料，第一材料和第二材料中的另一种是氮化碳化硅材料。 通过使用第一材料和第二材料，可以完全蚀刻通过第一蚀刻停止层以到达其下方形成的接触区域，而不完全蚀刻通过第二蚀刻停止层，以到达在其下方形成的第一介电层。

    Stress management of barrier metal for resolving CU line corrosion
    19.
    发明授权
    Stress management of barrier metal for resolving CU line corrosion 有权
    用于解决CU线腐蚀的隔离金属的应力管理

    公开(公告)号：US06297158B1

    公开(公告)日：2001-10-02

    申请号：US09583402

    申请日：2000-05-31

    申请人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

    发明人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

    IPC分类号： H01L214763

    CPC分类号： H01L21/76873 ,  H01L21/76843 ,  H01L21/76864

    摘要： In the presently disclosed invention, a method is provided to avoid damage to a copper interconnect while subjecting the interconnect to chemical-mechanical polishing (CMP). First, a copper barrier layer is formed in a damascene structure. Then, prior to the deposition of copper metal into the damascene openings, a barrier layer is formed on the inside walls of the damascene structure. In a first embodiment, the copper barrier layer is deposited at high temperature. Then, it is cooled down in a prescribed manner. Subsequently, a copper seed layer is formed over the barrier, which is followed by the electro-chemical deposition (ECD) of copper, to form the copper damascene interconnect. Alternatively, in a second embodiment, the copper layer is formed at low temperature. Then it is annealed at a high temperature, followed by wafer cooling. Subsequently, copper seed layer is formed over the barrier layer. Next, ECD copper is formed in the damascene structure. Finally, the interconnect so formed by either of the embodiments is subjected to CMP. It is found that, through the disclosed method of treatment of the barrier layer, process stresses that are normally formed within the barrier layer are relieved, and hence no damage is incurred during the final steps of chemical-mechanical polishing.

    摘要翻译： 在本公开的发明中，提供了一种方法，以避免对互连线进行化学机械抛光（CMP）的铜互连的损坏。 首先，在大马士革结构中形成铜阻挡层。 然后，在将铜金属沉积到镶嵌开口之前，在镶嵌结构的内壁上形成阻挡层。 在第一实施例中，铜阻挡层在高温下沉积。 然后，以规定的方式冷却。 随后，在屏障上形成铜籽晶层，随后是铜的电化学沉积（ECD），以形成铜镶嵌互连。 或者，在第二实施例中，铜层在低温下形成。 然后在高温下进行退火，然后进行晶片冷却。 随后，在阻挡层上形成铜籽晶层。 接下来，在镶嵌结构中形成ECD铜。 最后，将由这两个实施例形成的互连件进行CMP处理。 发现通过公开的阻挡层处理方法，通常在阻挡层内形成的工艺应力被释放，因此在化学机械抛光的最终步骤期间不会产生损伤。

    Method for improvement of gap filling capability of electrochemical deposition of copper
    20.
    发明授权
    Method for improvement of gap filling capability of electrochemical deposition of copper 有权
    改进铜电化学沉积间隙填充能力的方法

    公开(公告)号：US06224737B1

    公开(公告)日：2001-05-01

    申请号：US09377540

    申请日：1999-08-19

    申请人： Ming-Hsing Tsai ,  Wen-Jye Tsai ,  Shau-Lin Shue ,  Chen-Hua Yu

    发明人： Ming-Hsing Tsai ,  Wen-Jye Tsai ,  Shau-Lin Shue ,  Chen-Hua Yu

    IPC分类号： C25D502

    CPC分类号： H01L21/76877 ,  C25D3/38 ,  C25D5/48 ,  C25D7/123 ,  H01L21/2885 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor structure having a trench formed therein is provided. The semiconductor structure may be a substrate with an overlying interlevel metal dielectric layer having the trench. A voltage is applied to the trenched semiconductor inducing a bias field where there is a first field proximate the trench bottom and a second field, greater than the first field, proximate the trench's upper side walls and the semiconductor upper surface proximate the trench. The semiconductor structure is placed into an electroplating solution containing a predetermined concentration of brighteners and levelers. Because of the induced bias field, the brightener concentration is greater proximate the trench bottom and the leveler concentration is greater the trench's upper side walls and the semiconductor upper surface proximate the trench. A copper layer having a predetermined thickness is then electrolytically deposited within the trench in a “bottom-up” fashion and blanket fills the upper surface of the semiconductor structure. The structure may then be planarized by CMP to create a planarized copper filled trench.

    摘要翻译： 提供具有形成在其中的沟槽的半导体结构。 半导体结构可以是具有具有沟槽的上覆层间金属介电层的衬底。 电压被施加到沟槽半导体，其诱导偏置场，其中存在靠近沟槽底部的第一场和大于第一场，接近沟槽的上侧壁和靠近沟槽的半导体上表面的第二场。 将半导体结构放入含有预定浓度的增白剂和矫直剂的电镀溶液中。 由于感应偏压场，光滑剂浓度在沟槽底部附近较大，并且矫直剂浓度大于沟槽的上侧壁和接近沟槽的半导体上表面。 然后将具有预定厚度的铜层以“自下而上”的方式电解沉积在沟槽内，并且覆盖填充半导体结构的上表面。 然后可以通过CMP平面化该结构以产生平坦化的铜填充沟槽。