公开(公告)号：US07672161B2

公开(公告)日：2010-03-02

申请号：US11742371

申请日：2007-04-30

申请人： Ping Hou ,  Eugen Gershon ,  Michael A. Van Buskirk

发明人： Ping Hou ,  Eugen Gershon ,  Michael A. Van Buskirk

IPC分类号： G11C11/03

CPC分类号： G11C11/5642

摘要： Systems, methods, and/or devices that facilitate accessing data from memory are presented. An adaptive detection component can be employed to reduce or minimize detection error and distinguish information stored in memory cells during read operations. A decoder component can include the adaptive detection component, which can employ an adaptive Linde-Buzo-Gray (LBG) algorithm. The decoder component can receive information associated with a current level from a memory location during a read operation, and can analyze and process such information. The adaptive detection component can receive the processed information and, along with other information, can process such information using the iterative LBG algorithm until reconstruction levels and corresponding threshold levels are determined. Such reconstruction levels and/or threshold levels can be compared to the value associated with the information read from the memory location to determine the data value of the data in the memory location.

摘要翻译： 介绍了便于从存储器访问数据的系统，方法和/或设备。 可以采用自适应检测部件来减少或最小化检测误差，并且在读取操作期间区分存储在存储器单元中的信息。 解码器组件可以包括自适应检测组件，其可以采用自适应林德 - 布佐灰色（LBG）算法。 解码器组件可以在读取操作期间从存储器位置接收与当前级别相关联的信息，并且可以分析和处理这样的信息。 自适应检测组件可以接收经处理的信息，并且与其他信息一起可以使用迭代LBG算法来处理这样的信息，直到确定重建级别和对应的阈值级别为止。 可以将这样的重建级别和/或阈值级别与与从存储器位置读取的信息相关联的值进行比较，以确定存储器位置中的数据的数据值。

公开(公告)号：US06555436B2

公开(公告)日：2003-04-29

申请号：US10223195

申请日：2002-08-19

申请人： Mark T. Ramsbey ,  Jean Y. Yang ,  Hidehiko Shiraiwa ,  Michael A. Van Buskirk ,  David M. Rogers ,  Ravi Sunkavalli ,  Janet Wang ,  Narbeh Derhacobian ,  Yider Wu

发明人： Mark T. Ramsbey ,  Jean Y. Yang ,  Hidehiko Shiraiwa ,  Michael A. Van Buskirk ,  David M. Rogers ,  Ravi Sunkavalli ,  Janet Wang ,  Narbeh Derhacobian ,  Yider Wu

IPC分类号： H01L21336

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11573 ,  Y10S438/954 ,  Y10S438/981

摘要： One aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving the sequential or non-sequential steps of forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a gate dielectric in the periphery region; forming buried bitlines in the core region; and forming gates in the core region and the periphery region.

公开(公告)号：US06205074B1

公开(公告)日：2001-03-20

申请号：US09610764

申请日：2000-07-06

申请人： Michael A. Van Buskirk ,  Bhimachar Venkatesh

发明人： Michael A. Van Buskirk ,  Bhimachar Venkatesh

IPC分类号： G11C700

CPC分类号： G11C5/145 ,  G11C16/30

摘要： The present invention discloses methods and systems for generating a bias voltage during an Automatic Program Disturb Erase Verify (APDEV) operation in a memory device. During the APDEV operation, a predetermined supply voltage is generated by a regulated power supply. The predetermined supply voltage is directed to a temperature-compensated bias generator circuit. The temperature-compensated bias generator circuit is activated to generate the bias voltage based on the operating temperature of the memory device.

摘要翻译： 本发明公开了在存储器件中的自动程序干扰擦除验证（APDEV）操作期间产生偏置电压的方法和系统。 在APDEV操作期间，通过稳压电源产生预定的电源电压。 预定的电源电压被引导到温度补偿偏置发生器电路。 温度补偿偏置发生器电路被激活以基于存储器件的工作温度产生偏置电压。

公开(公告)号：US5847998A

公开(公告)日：1998-12-08

申请号：US769009

申请日：1996-12-20

申请人： Michael A. Van Buskirk

发明人： Michael A. Van Buskirk

IPC分类号： G11C8/16 ,  G11C16/10 ,  G11C16/26 ,  G11C16/02

CPC分类号： G11C8/16 ,  G11C16/10 ,  G11C16/26 ,  G11C2216/22

摘要： A non-volatile memory having a non-volatile memory array arranged as a plurality of sectors each containing an array of non-volatile memory cells. The non-volatile memory includes independent read and write paths and selection circuitry for each sector that enables a read operation from one of the sectors during a program or erase operation to one of the other sectors.

摘要翻译： 一种非易失性存储器，其具有排列成多个扇区的非易失性存储器阵列，每个扇区都包含非易失性存储单元阵列。 非易失性存储器包括用于每个扇区的独立的读取和写入路径和选择电路，其能够在对其他扇区之一进行编程或擦除操作期间从扇区中的一个读取操作。

公开(公告)号：US5650964A

公开(公告)日：1997-07-22

申请号：US486192

申请日：1995-06-07

申请人： Jian Chen ,  James J. Hsu ,  Shengwen Luan ,  Yuan Tang ,  David Kuan-Yu Liu ,  Michael A. Van Buskirk

发明人： Jian Chen ,  James J. Hsu ,  Shengwen Luan ,  Yuan Tang ,  David Kuan-Yu Liu ,  Michael A. Van Buskirk

IPC分类号： G11C16/14 ,  G11C16/04

CPC分类号： G11C16/14

摘要： A process for discharging a floating gate semiconductor device formed in a semiconductor substrate, the device having a first active region, a second active region, a charge holding region, and a channel between the first and second active regions, the channel having a length defined by a distance below the charge holding region between the first and second active regions. The process comprises the steps of: applying a first positive voltage of about 4-8 volts to the first active region; applying a second voltage in the range of about 0.5-3 volts to the second active region; applying a third voltage in the range of minus 8 volts to the charge holding region; and coupling the substrate to ground. The first active region may comprise either a source or a drain region of a MOSFET, and the second active region may comprise a source region or a drain region of a MOSFET. In a further aspect an array of floating gate transistors, each transistor comprising a source, drain, gate and floating gate, each floating gate including an electric charge; and control logic coupled to the transistors, for selectively addressing the transistors is disclosed. In the apparatus, to discharge the floating gates of each transistor in the array: each source is coupled in common to a first voltage; each drain is coupled in common to a second voltage lower than the first voltage; the substrate is coupled to ground; and each floating gate is coupled to a negative voltage.

摘要翻译： 一种用于对形成在半导体衬底中的浮栅半导体器件进行放电的工艺，该器件具有第一有源区，第二有源区，电荷保持区和在第一和第二有源区之间的沟道， 在第一和第二有源区域之间的电荷保持区域之下的距离处。 该方法包括以下步骤：向第一有源区施加约4-8伏特的第一正电压; 向第二活动区域施加约0.5-3伏特范围内的第二电压; 将负8伏范围内的第三电压施加到电荷保持区; 并将衬底耦合到地面。 第一有源区可以包括MOSFET的源极或漏极区域，并且第二有源区域可以包括MOSFET的源极区域或漏极区域。 在另一方面，一种浮动栅极晶体管阵列，每个晶体管包括源极，漏极，栅极和浮置栅极，每个浮置栅极包括电荷; 并且公开了耦合到晶体管的控制逻辑，用于选择性寻址晶体管。 在该装置中，为了排出阵列中每个晶体管的浮置栅极：每个源极共同耦合到第一电压; 每个漏极共同耦合到低于第一电压的第二电压; 衬底耦合到地面; 并且每个浮动栅极耦合到负电压。

公开(公告)号：US5349558A

公开(公告)日：1994-09-20

申请号：US112033

申请日：1993-08-26

申请人： Lee E. Cleveland ,  Michael A. Van Buskirk ,  Johnny C. Chen ,  Chung K. Chang

发明人： Lee E. Cleveland ,  Michael A. Van Buskirk ,  Johnny C. Chen ,  Chung K. Chang

IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04 ,  H01L21/8247 ,  H01L27/115 ,  G11C7/00

CPC分类号： G11C29/808

摘要： An improved redundancy architecture is provided for an array of flash EEPROM cells which permit repair of defective columns of memory cells in the array with redundant columns of memory cells on a sector-by-sector basis. The redundancy circuitry includes a plurality of sector-based redundancy blocks (2-8) each having redundant columns of memory cells extending through the plurality of sectors. Sector selection transistors (Q1,Q2) are provided for dividing the redundant columns into different segments, each residing in at least one of the plurality of sectors and for isolating the different segments so as to allow independent use from other segments in the same redundant column in repairing defective columns in the corresponding ones of the plurality of sectors. Addressable storage circuitry (314a,314b) is used for storing sector-based redundancy column addresses, each defining a column address containing the defective column of memory cells in the plurality of sectors in association with one of the different redundant column segments to be used in repairing the defective column.

摘要翻译： 提供了一种用于快闪EEPROM单元阵列的改进的冗余架构，其允许以扇区为基础以冗余列的存储器单元来修复阵列中的存储器单元的有缺陷的列。 冗余电路包括多个基于扇区的冗余块（2-8），每个冗余块具有延伸穿过多个扇区的多个存储单元冗余列。 扇区选择晶体管（Q1，Q2）被提供用于将冗余列分成不同的段，每个段驻留在多个扇区中的至少一个扇区中，并且用于隔离不同的段，以允许独立使用同一冗余列中的其他段 在修复多个扇区中相应的扇区中的有缺陷的列。 可寻址存储电路（314a，314b）用于存储基于扇区的冗余列地址，每个定义包含多个扇区中的存储单元的缺陷列的列地址，与不同冗余列段之一相关联地使用 修理有缺陷的列。

公开(公告)号：US09559216B2

公开(公告)日：2017-01-31

申请号：US13153707

申请日：2011-06-06

申请人： Srinivasa Rao Banna ,  Michael A. Van Buskirk ,  Timothy Thurgate

发明人： Srinivasa Rao Banna ,  Michael A. Van Buskirk ,  Timothy Thurgate

IPC分类号： G11C16/04 ,  H01L29/792 ,  H01L27/115

CPC分类号： H01L29/792 ,  G11C16/0416 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11582

摘要： Techniques for providing a semiconductor memory device are disclosed. In one particular embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region coupled to a source line, a second region coupled to a bit line, and a body region capacitively coupled to at least one word line via a tunneling insulating layer and disposed between the first region and the second region.

摘要翻译： 公开了一种用于提供半导体存储器件的技术。 在一个具体实施例中，这些技术可以被实现为包括以行和列的阵列布置的多个存储单元的半导体存储器件。 每个存储器单元可以包括耦合到源极线的第一区域，耦合到位线的第二区域和经由隧道绝缘层电容耦合到至少一个字线并且设置在第一区域和第二区域之间的体区域 。

公开(公告)号：US08624219B1

公开(公告)日：2014-01-07

申请号：US13445389

申请日：2012-04-12

申请人： John Ross Jameson ,  Antonio R. Gallo ,  Foroozan Sarah Koushan ,  Michael A. Van Buskirk

发明人： John Ross Jameson ,  Antonio R. Gallo ,  Foroozan Sarah Koushan ,  Michael A. Van Buskirk

IPC分类号： H01L47/00

CPC分类号： H01L45/085 ,  H01L45/122

摘要： A memory device can include at least one cathode formed in first opening of a first insulating layer; at least one anode formed in a second opening of second insulating layer, the second insulating layer being a different vertical layer than the first insulating layer; and a memory layer comprising an ion conductor layer extending laterally between the at least one anode and cathode on the first insulating layer, the ion conductor layer having a thickness in the vertical direction less than a depth of the first opening.

摘要翻译： 存储器件可以包括形成在第一绝缘层的第一开口中的至少一个阴极; 形成在第二绝缘层的第二开口中的至少一个阳极，所述第二绝缘层是与所述第一绝缘层不同的垂直层; 以及存储层，其包括在所述第一绝缘层上的所述至少一个阳极和阴极之间横向延伸的离子导体层，所述离子导体层的垂直方向的厚度小于所述第一开口的深度。

公开(公告)号：US20120307568A1

公开(公告)日：2012-12-06

申请号：US13153707

申请日：2011-06-06

申请人： Srinivasa Rao Banna ,  Michael A. Van Buskirk ,  Timothy Thurgate

发明人： Srinivasa Rao Banna ,  Michael A. Van Buskirk ,  Timothy Thurgate

IPC分类号： G11C16/10 ,  G11C16/04 ,  H01L29/792

CPC分类号： H01L29/792 ,  G11C16/0416 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11582

摘要： Techniques for providing a semiconductor memory device are disclosed. In one particular embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region coupled to a source line, a second region coupled to a bit line, and a body region capacitively coupled to at least one word line via a tunneling insulating layer and disposed between the first region and the second region.

摘要翻译： 公开了一种用于提供半导体存储器件的技术。 在一个具体实施例中，这些技术可以被实现为包括以行和列的阵列布置的多个存储单元的半导体存储器件。 每个存储器单元可以包括耦合到源极线的第一区域，耦合到位线的第二区域和经由隧道绝缘层电容耦合到至少一个字线并且设置在第一区域和第二区域之间的体区域 。

公开(公告)号：US07902086B2

公开(公告)日：2011-03-08

申请号：US11608388

申请日：2006-12-08

申请人： Swaroop Kaza ,  David Gaun ,  Michael A. Van Buskirk

发明人： Swaroop Kaza ,  David Gaun ,  Michael A. Van Buskirk

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L51/0575 ,  G11C13/0014 ,  G11C13/0016 ,  G11C2213/51 ,  G11C2213/77 ,  H01L27/285

摘要： Improving memory retention properties of a polymer memory cell are disclosed. The methods include providing a semiconducting polymer layer containing at least one organic semiconductor and at least one of a carrier ion oxidation preventer and an electrode oxidation preventer. The oxidation preventers may contain at least one of 1) an oxygen scavenger, 2) a polymer with oxidizable side-chain groups which can be preferentially oxidized over the carrier ions/electrodes, and 3) an oxidizable molecule that can be preferentially oxidized over the carrier ions/electrodes.

摘要翻译： 公开了提高聚合物存储器单元的记忆保持性能。 所述方法包括提供含有至少一种有机半导体和载流子离子氧化防止剂和电极氧化防止剂中的至少一种的半导体聚合物层。 氧化防止剂可以含有1）除氧剂中的至少一种，2）具有可氧化的侧链基团的聚合物，其可以优先在载体离子/电极上氧化，和3）可以优先氧化的可氧化分子 载体离子/电极。