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    APPARATUSES AND METHODS FOR CONCURRENTLY ACCESSING DIFFERENT MEMORY PLANES OF A MEMORY
    11.
    发明申请
    APPARATUSES AND METHODS FOR CONCURRENTLY ACCESSING DIFFERENT MEMORY PLANES OF A MEMORY 审中-公开
    用于同时访问存储器的不同存储器的设备和方法

    公开(公告)号：US20160026565A1

    公开(公告)日：2016-01-28

    申请号：US14340976

    申请日：2014-07-25

    申请人： Micron Technology, Inc.

    发明人： Tommaso Vali ,  Andrea Giovanni Xotta ,  Umberto Siciliani ,  Luca DeSantis ,  Michele Incarnati

    IPC分类号： G06F12/06 ,  G06F12/02

    CPC分类号： G06F12/0646 ,  G06F12/023 ,  G06F12/0238 ,  G06F2212/1016 ,  G06F2212/251 ,  G06F2212/7208

    摘要： Apparatuses and methods for concurrently accessing different memory planes are disclosed herein. An example apparatus may include a controller associated with a queue configured to maintain respective information associated with each of a plurality of memory command and address pairs. The controller is configured to select a group of memory command and address pairs from the plurality of memory command and address pairs based on the information maintained by the queue. The example apparatus further includes a memory configured to receive the group of memory command and address pairs. The memory is configured to concurrently perform memory access operations associated with the group of memory command and address pairs.

    摘要翻译： 本文公开了同时访问不同存储器平面的装置和方法。 示例性设备可以包括与被配置为维护与多个存储器命令和地址对中的每一个相关联的相应信息的队列相关联的控制器。 控制器被配置为基于由队列维护的信息从多个存储器命令和地址对中选择一组存储器命令和地址对。 该示例设备还包括被配置为接收该组存储器命令和地址对的存储器。 存储器被配置为同时执行与该组存储器命令和地址对相关联的存储器访问操作。

    CROSS-TEMPERATURE COMPENSATION IN A MEMORY SUB-SYSTEM
    12.
    发明公开
    CROSS-TEMPERATURE COMPENSATION IN A MEMORY SUB-SYSTEM 审中-公开

    公开(公告)号：US20240071427A1

    公开(公告)日：2024-02-29

    申请号：US18237816

    申请日：2023-08-24

    申请人： Micron Technology, Inc.

    发明人： Andrea Giovanni Xotta ,  Umberto Siciliani ,  Tommaso Vali

    IPC分类号： G11C7/04 ,  G11C7/10

    CPC分类号： G11C7/04 ,  G11C7/1069 ,  G11C7/1096

    摘要： Control logic in a memory device receives, from a requestor, a request to read data from the memory array, the request comprising an indication of a segment of the memory array where the data is stored and performs, using previously configured read operation parameters, a first read operation to read the data and a write temperature associated with the data from the memory array. The control logic determines whether the previously configured read operation parameters satisfy a temperature criterion and responsive to determining that the previously configured read operation parameters do not satisfy the temperature criterion, configures the memory device with updated read operation parameters, and performs, using the updated read operation parameters, a second read operation to read the data from the memory array.

    Asynchronous interrupt event handling in multi-plane memory devices
    13.
    发明授权
    Asynchronous interrupt event handling in multi-plane memory devices 有权

    公开(公告)号：US11842078B2

    公开(公告)日：2023-12-12

    申请号：US17589080

    申请日：2022-01-31

    申请人： Micron Technology, Inc.

    发明人： Andrea Giovanni Xotta ,  Guido Luciano Rizzo ,  Umberto Siciliani ,  Tommaso Vali ,  Luca De Santis ,  Walter Di Francesco

    IPC分类号： G06F12/00 ,  G06F3/06 ,  G06F9/48

    CPC分类号： G06F3/0659 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0679 ,  G06F9/4812

    摘要： A memory device includes a memory array configured with a plurality of memory planes, and control logic, operatively coupled with the memory array. The control logic performs a plurality of asynchronous memory access operations on the plurality of memory planes, detects an occurrence of an asynchronous interrupt event, and initiates a termination procedure for each of the plurality of asynchronous memory access operations to permit each of the plurality of asynchronous memory access operations to end at different times. In response to a first memory access operation of the plurality of asynchronous memory access operations ending, the control logic asserts a command result signal, wherein the command result signal is de-asserted automatically in response to receipt of a subsequent memory access command directed to any of the plurality of memory planes, and asserts a persistent event register signal, wherein the command result signal is de-asserted in response to receipt of a clear event register command.

    ASYNCHRONOUS INTERRUPT EVENT HANDLING IN MULTI-PLANE MEMORY DEVICES
    16.
    发明申请
    ASYNCHRONOUS INTERRUPT EVENT HANDLING IN MULTI-PLANE MEMORY DEVICES 有权

    公开(公告)号：US20220405013A1

    公开(公告)日：2022-12-22

    申请号：US17589080

    申请日：2022-01-31

    申请人： Micron Technology, Inc.

    发明人： Andrea Giovanni Xotta ,  Guido Luciano Rizzo ,  Umberto Siciliani ,  Tommaso Vali ,  Luca De Santis ,  Walter Di Francesco

    IPC分类号： G06F3/06 ,  G06F9/48

    摘要： A memory device includes a memory array configured with a plurality of memory planes, and control logic, operatively coupled with the memory array. The control logic performs a plurality of asynchronous memory access operations on the plurality of memory planes, detects an occurrence of an asynchronous interrupt event, and initiates a termination procedure for each of the plurality of asynchronous memory access operations to permit each of the plurality of asynchronous memory access operations to end at different times. In response to a first memory access operation of the plurality of asynchronous memory access operations ending, the control logic asserts a command result signal, wherein the command result signal is de-asserted automatically in response to receipt of a subsequent memory access command directed to any of the plurality of memory planes, and asserts a persistent event register signal, wherein the command result signal is de-asserted in response to receipt of a clear event register command.