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    DATA MASKING FOR MEMORY
    13.
    发明申请
    DATA MASKING FOR MEMORY 有权

    公开(公告)号：US20240419338A1

    公开(公告)日：2024-12-19

    申请号：US18749391

    申请日：2024-06-20

    Applicant: Micron Technology, Inc.

    Inventor： Angelo Visconti ,  Jahanshir Javanifard ,  Daniele Vimercati

    IPC: G06F3/06

    Abstract: Methods, systems, and devices for data masking for memory are described. A memory device may set multiple data masking flags for associated memory array(s) at power-up. Each data masking flag may be associated with a respective page of memory cells and may indicate whether the data stored in the respective page is masked data, or whether the data is new, unmasked data. Data existing at a previous power-down may be masked until an initial write or activate command has been performed on the page after power-up, where the initial write or activate command may result in writing masked data, write data, or a combination thereof to the page. After previously stored data is overwritten to a page, the flag associated with the page may be reset, which may indicate that data stored at the page is available to be read.

    Apparatuses, systems, and methods for configurable memory
    14.
    发明授权
    Apparatuses, systems, and methods for configurable memory 有权

    公开(公告)号：US12112785B2

    公开(公告)日：2024-10-08

    申请号：US17732885

    申请日：2022-04-29

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Angelo Visconti ,  Giorgio Servalli

    IPC: G11C11/22

    CPC classification number: G11C11/2255 ,  G11C11/221 ,  G11C11/2273

    Abstract: At least one portion of a memory array may be arranged to provide high density non-volatile random access memory (HIGH DENSITY NON-VOLATILE RAM) while at least one other portion of the memory array may be arranged to provide dynamic random access memory (DRAM)-like memory. In some examples, the memory array may be arranged by programming one or more configuration devices. In some examples, the configuration device may include one or more switches to couple one or more memory cells to a sense amplifier. In some examples, the configuration device may include fuses and/or antifuses to couple one or more memory cells to a sense amplifier. In some examples, the portions of the memory array may be reconfigurable from one arrangement to another arrangement.

    SWITCH AND HOLD BIASING FOR MEMORY CELL IMPRINT RECOVERY
    16.
    发明公开
    SWITCH AND HOLD BIASING FOR MEMORY CELL IMPRINT RECOVERY 审中-公开

    公开(公告)号：US20230395114A1

    公开(公告)日：2023-12-07

    申请号：US17830100

    申请日：2022-06-01

    Applicant: Micron Technology, Inc.

    Inventor： Angelo Visconti

    IPC: G11C11/22

    CPC classification number: G11C11/2297 ,  G11C11/221

    Abstract: Methods, systems, and devices for switch and hold biasing for memory cell imprint recovery are described. A memory device may be configured to perform an imprint recovery procedure that includes applying one or more recovery pulses to memory cells, where each recovery pulse is associated with a voltage polarity and includes a first portion with a first voltage magnitude and a second portion with a second voltage magnitude that is lower than the first voltage magnitude. In some examples, the first voltage magnitude may correspond to a voltage that imposes a saturation polarization on a memory cell (e.g., on a ferroelectric capacitor, a polarization corresponding to the associated voltage polarity) and the second voltage magnitude may correspond to a voltage magnitude that is high enough to maintain the saturation polarization (e.g., to prevent a reduction of polarization) of the memory cell.

    Memory management for charge leakage in a memory device
    17.
    发明授权
    Memory management for charge leakage in a memory device 有权

    公开(公告)号：US11688449B2

    公开(公告)日：2023-06-27

    申请号：US17208470

    申请日：2021-03-22

    Applicant: Micron Technology, Inc.

    Inventor： Angelo Visconti

    IPC: G11C11/22 ,  G11C11/4091

    CPC classification number: G11C11/2275 ,  G11C11/221 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/4091

    Abstract: Methods, systems, and devices for memory management associated with charge leakage in a memory device are described. A memory device may identify a charge leakage associated with one or more memory cells or access lines, and may determine whether to invert a logic state stored by a memory cell or a set of memory cells to improve the likelihood that the memory cells are read properly in the presence of charge leakage. In some examples, the memory device may also store an indication that the complement of the detected logic state was written, such as a bit flip indication, which may correspond to one memory cell or a set of memory cells.

    Open page biasing techniques
    18.
    发明授权
    Open page biasing techniques 有权

    公开(公告)号：US11189330B2

    公开(公告)日：2021-11-30

    申请号：US17143800

    申请日：2021-01-07

    Applicant: Micron Technology, Inc.

    Inventor： Angelo Visconti ,  Andrea Locatelli ,  Giorgio Servalli

    IPC: G11C11/22 ,  G06F3/06

    Abstract: Methods, systems, and devices for biasing techniques, such as open page biasing techniques, are described. A memory cell may be accessed during an access phase of an access operation, for example, an open page access operation. An activate pulse may be applied to the memory cell during the access phase. The memory cell may be biased to a non-zero voltage after applying the activate pulse and before a pre-charge phase. The pre-charge phase of the access phase may be initiated after biasing the memory cell to the non-zero voltage.

    MEMORY CELL BIASING TECHNIQUES
    19.
    发明申请
    MEMORY CELL BIASING TECHNIQUES 有权

    公开(公告)号：US20210264961A1

    公开(公告)日：2021-08-26

    申请号：US17196661

    申请日：2021-03-09

    Applicant: Micron Technology, Inc.

    Inventor： Angelo Visconti ,  Giorgio Servalli ,  Andrea Locatelli

    IPC: G11C11/22 ,  G06F3/06

    Abstract: Methods, systems, and devices for memory cell biasing techniques are described. A memory cell may be accessed during an access phase of an access operation. A pre-charge phase of the access phase may be initiated. The memory cell may be biased to a voltage (e.g., a non-zero voltage) after the pre-charge phase. In some examples, the memory cell may be biased to the voltage when a word line is unbiased and the memory cell is isolated from the digit line.

    Read operations based on a dynamic reference
    20.
    发明授权
    Read operations based on a dynamic reference 有权

    公开(公告)号：US11056178B1

    公开(公告)日：2021-07-06

    申请号：US16933829

    申请日：2020-07-20

    Applicant: Micron Technology, Inc.

    Inventor： Ferdinando Bedeschi ,  Umberto Di Vincenzo ,  Riccardo Muzzetto ,  Angelo Visconti

    IPC: G11C7/06 ,  G11C11/4091 ,  G11C11/4074 ,  G11C11/404 ,  G11C11/4099 ,  G11C11/22 ,  G11C11/24

    Abstract: Methods, systems, and devices for read operations based on a dynamic reference are described. A memory device may include a set of memory cells each associated with a capacitive circuit including a first and second capacitor. After receiving a read command, the memory device may couple each capacitive circuit with a respective memory cell (e.g., to transfer a charge stored by each respective memory cell to a capacitive circuit) and may couple the second capacitor of each capacitive circuit to a reference voltage bus. Thus, a reference voltage on the reference voltage bus may be based on an average charge across the second capacitors of each capacitive circuit. The memory device may then compare a charge stored by the first and second capacitors of each capacitive circuit with the reference voltage bus and may output a set of values stored by the set of memory cells based on the comparing.

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