公开(公告)号：US20210043504A1

公开(公告)日：2021-02-11

申请号：US16532035

申请日：2019-08-05

Applicant: Micron Technology, Inc.

Inventor： Anilkumar Chandolu ,  Christopher R. Ritchie ,  Darwin A. Clampitt ,  S M Istiaque Hossain

IPC: H01L21/768 ,  H01L27/11556 ,  H01L27/11582

Abstract: A method of forming a microelectronic device comprises forming a stack structure comprising vertically alternating insulating structures and additional insulating structures arranged in tiers. Each of the tiers individually comprises one of the insulating structures and one of the additional insulating structures. A first trench is formed to partially vertically extend through the stack structure. The first trench comprises a first portion having a first width, and a second portion at a horizontal boundary of the first portion and having a second width greater than the first width. A dielectric structure is formed within the first trench. The dielectric structure comprises a substantially void-free section proximate the horizontal boundary of the first portion of the trench. Microelectronic devices and electronic systems are also described.

公开(公告)号：US10658380B2

公开(公告)日：2020-05-19

申请号：US16160146

申请日：2018-10-15

Applicant: Micron Technology, Inc.

Inventor： Matthew J. King ,  Anilkumar Chandolu ,  Indra V. Chary ,  Darwin A. Clampitt ,  Gordon Haller ,  Thomas George ,  Brett D. Lowe ,  David A. Daycock

IPC: H01L27/115 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11573

Abstract: In an example, a method of forming a stacked memory array includes forming a stack of alternating first and second dielectrics, forming a termination structure through the stack, the termination structure comprising a dielectric liner around a conductor, forming a set of contacts concurrently with forming the termination structure, forming a third dielectric over an upper surface of the stack and an upper surface of the termination structure, forming a first opening through the third dielectric and the stack between first and second groups of semiconductor structures so that the first opening exposes an upper surface of the conductor, and removing the conductor from the termination structure to form a second opening lined with the dielectric liner. In some examples, the dielectric liner can include a rectangular or a triangular tab or a pair of prongs that can have a rectangular profile or that can be tapered.

公开(公告)号：US20250006261A1

公开(公告)日：2025-01-02

申请号：US18746904

申请日：2024-06-18

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Collin Howder

IPC: G11C16/04 ,  G11C16/14 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: A variety of applications can include memory devices designed to provide enhanced gate-induced-drain-leakage (GIDL) current during memory erase operations. The enhanced operation can be provided by enhancing the electric field in the channel structures of select gate transistors to strings of memory cells at segmented drains of the select gate transistors. The segmented drains can have conductive fins integrated with the transistor channel structure and extending vertically from a top border of the transistor channel structure, where the conductive fins are separated from each other by non-conductive regions on the top border. The segmented drain can include portions extending downward below the top border. The transistor channel structures can be integrated with the channel structures of the pillars forming the strings of memory cells. Additional devices, systems, and methods are discussed.

公开(公告)号：US20240379544A1

公开(公告)日：2024-11-14

申请号：US18654618

申请日：2024-05-03

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Martin Jared Barclay ,  Haoyu Li

IPC: H01L23/528 ,  H01L21/768 ,  H10B41/27 ,  H10B43/27

Abstract: Methods, systems, and devices for low resistance staircase rivet contact using metal-to-metal strap connection are described. The described techniques provide for usage of a metallic material that adheres to a dielectric material when deposited via a chemical vapor deposition (CVD) process or atomic layer deposition (ALD) process to connect to a word line contact. For example, a strap may be formed between a layer of conductive material and a word line contact that extends at least partially through a stack of layers, and may be filled with such a metallic material. Such techniques may support a connection between the word line contact and the layer of conductive material without usage of a liner material, which may mitigate a resistance of the connection.

公开(公告)号：US20240304722A1

公开(公告)日：2024-09-12

申请号：US18424704

申请日：2024-01-26

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Roger W. Lindsay ,  Martin J. Barclay

IPC: H01L29/78 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L29/7827 ,  H10B41/27 ,  H10B43/27

Abstract: A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, a staircase structure comprising steps comprising horizontal edges of the tiers, each of the steps comprising multiple tiers, and conductive contact structures vertically extending from a vertically upper surface of the stack structure to the conductive structures of the steps, the conductive structures defining each of the steps individually in contact with a conductive contact structure. Related memory devices and electronic systems are also described.

公开(公告)号：US20240268118A1

公开(公告)日：2024-08-08

申请号：US18435116

申请日：2024-02-07

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Patrick White ,  Kevin Y. Titus ,  Steven P. Turini

IPC: H10B43/27 ,  H01L21/02 ,  H01L21/67 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L21/0217 ,  H01L21/67063 ,  H10B43/35 ,  H10B43/40

Abstract: A method used in forming memory circuitry comprises forming a stack where strings of memory cells will be formed and a select-gate region directly above the stack. The stack comprises vertically-alternating different-composition first tiers and second tiers having lower channel openings extending there-through. The select-gate region comprises upper channel openings extending there-through and that are individually directly above and extend to individual of the lower channel openings. Storage material of the strings of memory cells is formed simultaneously in the upper and lower channel openings. Then, insulative charge-passage material of the strings of memory cells is formed simultaneously in the upper and lower channel openings. Then, channel material is formed simultaneously in the upper and lower channel openings. The storage material is removed from the upper channel openings. After the removing, a select gate is formed in the select-gate region operatively aside the channel material in the select-gate region. Other embodiments, including structure, are disclosed.

公开(公告)号：US20240170066A1

公开(公告)日：2024-05-23

申请号：US18509517

申请日：2023-11-15

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  John D. Hopkins

IPC: G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: Memory circuitry comprising strings of memory cells comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers extend from the memory-array region into a stair-step region. The stair-step region comprises a flight of stairs. The stairs individually comprise a tread comprising conducting material of one of the conductive tiers. A conductive-via construction extends downwardly from and directly below the conducting material of individual of the treads to circuitry that is directly below the stack. The conductive-via construction comprises an insulator lining circumferentially about conductor material. The insulator lining and the conductor material extend downwardly from the individual treads through that portion of the stack that is directly thereunder. The conductor material electrically couples with the circuitry that is directly below the stack. The conducting material of the individual treads is directly electrically coupled to the conductor material of individual of the conductive-via constructions. Methods are also disclosed.

公开(公告)号：US11942422B2

公开(公告)日：2024-03-26

申请号：US18050438

申请日：2022-10-27

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Roger W. Lindsay ,  Jeffrey D. Runia ,  Matthew Holland ,  Chamunda N. Chamunda

IPC: H01L23/522 ,  G11C7/18 ,  G11C8/14 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L23/5226 ,  G11C7/18 ,  G11C8/14 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A microelectronic device comprises a stack structure, a stadium structure within the stack structure, and conductive contact structures. The stack structure comprises a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. Each of the tiers comprises one of the conductive structures and one of the insulative structures. The stadium structure comprises a forward staircase structure having steps comprising edges of the tiers, and a reverse staircase structure opposing the forward staircase structure and having additional steps comprising additional edges of the tiers. The conductive contact structures vertically extend to upper vertical boundaries of at least some of the conductive structures of the stack structure at the steps of the forward staircase structure and the additional steps of the reverse staircase structure, and are each integral and continuous with one of the conductive structures. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

公开(公告)号：US20240079322A1

公开(公告)日：2024-03-07

申请号：US17930365

申请日：2022-09-07

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Shruthi Kumara Vadivel ,  David Neumeyer

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/535

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76895 ,  H01L23/535

Abstract: A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, the stack structure divided into block structures horizontally extending in parallel in a first direction and horizontally separated from one another in a second direction by dielectric slot structures. At least one of the block structures comprises a stadium structure comprising opposing staircase structures each having steps comprising edges of the tiers, and conductive contact structures vertically extending to and in contact with at least some of the conductive structures at the steps, the conductive contact structures positioned proximate horizontal boundaries of the stadium structure in the second direction. Related memory devices, electronic systems, and methods are also described.

公开(公告)号：US20230397419A1

公开(公告)日：2023-12-07

申请号：US17816651

申请日：2022-08-01

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Wesley O. Mckinsey ,  John Hopkins

IPC: H01L27/11582 ,  G11C16/04 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  H01L27/11556

Abstract: For manufacturing a memory device, a system may form a trench between a first portion and a second portion of a stack. A bottom wall of the trench may include a spacer material. The system may remove a first and a second oxide material to reform the trench, and remove a polysilicon material in a lateral direction to expose a third oxide material and a channel structure. The third oxide material may form the bottom wall of the trench. The system may remove, in a lateral direction, the first oxide material, a portion of the second oxide material, the third oxide material, and a fourth oxide material of the channel structure. The system may deposit a metal material, in the trench, in contact with a doped polysilicon material of the channel structure.