公开(公告)号：US11177279B2

公开(公告)日：2021-11-16

申请号：US16876896

申请日：2020-05-18

Applicant: Micron Technology, Inc.

Inventor： Matthew J. King ,  Anilkumar Chandolu ,  Indra V. Chary ,  Darwin A. Clampitt ,  Gordon Haller ,  Thomas George ,  Brett D. Lowe ,  David A. Daycock

IPC: H01L27/115 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11573

Abstract: In an example, a method of forming a stacked memory array includes forming a stack of alternating first and second dielectrics, forming a termination structure through the stack, the termination structure comprising a dielectric liner around a conductor, forming a set of contacts concurrently with forming the termination structure, forming a third dielectric over an upper surface of the stack and an upper surface of the termination structure, forming a first opening through the third dielectric and the stack between first and second groups of semiconductor structures so that the first opening exposes an upper surface of the conductor, and removing the conductor from the termination structure to form a second opening lined with the dielectric liner. In some examples, the dielectric liner can include a rectangular or a triangular tab or a pair of prongs that can have a rectangular profile or that can be tapered.

公开(公告)号：US20200279867A1

公开(公告)日：2020-09-03

申请号：US16876896

申请日：2020-05-18

Applicant: Micron Technology, Inc.

Inventor： Matthew J. King ,  Anilkumar Chandolu ,  Indra V. Chary ,  Darwin A. Clampitt ,  Gordon Haller ,  Thomas George ,  Brett D. Lowe ,  David A. Daycock

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11573

Abstract: In an example, a method of forming a stacked memory array includes forming a stack of alternating first and second dielectrics, forming a termination structure through the stack, the termination structure comprising a dielectric liner around a conductor, forming a set of contacts concurrently with forming the termination structure, forming a third dielectric over an upper surface of the stack and an upper surface of the termination structure, forming a first opening through the third dielectric and the stack between first and second groups of semiconductor structures so that the first opening exposes an upper surface of the conductor, and removing the conductor from the termination structure to form a second opening lined with the dielectric liner. In some examples, the dielectric liner can include a rectangular or a triangular tab or a pair of prongs that can have a rectangular profile or that can be tapered.

公开(公告)号：US20250048614A1

公开(公告)日：2025-02-06

申请号：US18745962

申请日：2024-06-17

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  David A. Daycock ,  Christopher K. Morzano

IPC: H10B12/00

Abstract: A microelectronic device comprises a first transistor structure comprising multiple vertical levels of channel regions, a second transistor structure neighboring the first transistor structure and comprising additional multiple vertical levels of channel regions, a storage device vertically overlying the first transistor structure and the second transistor structure, a first conductive contact structure contacting the first transistor structure, and a second conductive contact structure contacting the second transistor structure. Related memory devices and electronic systems are also described.

公开(公告)号：US11967556B2

公开(公告)日：2024-04-23

申请号：US17452113

申请日：2021-10-25

Applicant: Micron Technology, Inc.

Inventor： Biow Hiem Ong ,  David A. Daycock ,  Chieh Hsien Quek ,  Chii Wean Calvin Chen ,  Christian George Emor ,  Wing Yu Lo

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H10B41/27 ,  H10B41/40 ,  H10B43/27

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53266 ,  H10B41/40 ,  H10B41/27 ,  H10B43/27

Abstract: Methods for forming microelectronic devices include forming a staircase structure in a stack structure having a vertically alternating sequence of insulative and conductive materials arranged in tiers. Steps are at lateral ends of the tiers. Contact openings of different aspect ratios are formed in fill material adjacent the staircase structure, with some openings terminating in the fill material and others exposing portions of the conductive material of upper tiers of the stack structure. Additional conductive material is selectively formed on the exposed portions of the conductive material. The contact openings initially terminating in the fill material are extended to expose portions of the conductive material of lower elevations. Contacts are formed, with some extending to the additional conductive material and others extending to conductive material of the tiers of the lower elevations. Microelectronic devices and systems incorporating such staircase structures and contacts are also disclosed.

公开(公告)号：US20230380193A1

公开(公告)日：2023-11-23

申请号：US18365850

申请日：2023-08-04

Applicant: Micron Technology, Inc.

Inventor： David A. Daycock ,  Jonghun Kim

IPC: H10B63/00 ,  H10N70/00

CPC classification number: H10B63/84 ,  H10N70/023 ,  H10N70/026 ,  H10N70/881 ,  H10N70/8265

Abstract: A method of forming an electronic device comprises forming a stack structure comprising vertically alternating insulative structures and additional insulative structures, and forming pillars comprising a channel material and at least one dielectric material vertically extending through the stack structure. The method comprises removing the additional insulative structures to form cell openings, forming a first conductive material within a portion of the cell openings, and forming a fill material adjacent to the first conductive material and within the cell openings. The fill material comprises sacrificial portions. The method comprises removing the sacrificial portions of the fill material, and forming a second conductive material within the cell openings in locations previously occupied by the sacrificial portions of the fill material. Related electronic devices, memory devices, and systems are also described.

公开(公告)号：US20220262820A1

公开(公告)日：2022-08-18

申请号：US17661659

申请日：2022-05-02

Applicant: Micron Technology, Inc.

Inventor： Matthew J. King ,  David A. Daycock ,  Yoshiaki Fukuzumi ,  Albert Fayrushin ,  Richard J. Hill ,  Chandra S. Tiwari ,  Jun Fujiki

IPC: H01L27/11582 ,  H01L29/06 ,  H01L21/762

Abstract: Microelectronic devices include a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A series of pillars extends through the stack structure. At least one isolation structure extends through an upper stack portion of the stack structure. The at least one isolation structure protrudes into pillars of neighboring columns of pillars of the series of pillars. Conductive contacts are in electrical communication with the pillars into which the at least one isolation structure protrudes. Related methods and electronic systems are also disclosed.

公开(公告)号：US11355607B2

公开(公告)日：2022-06-07

申请号：US14875493

申请日：2015-10-05

Applicant: Micron Technology, Inc.

Inventor： Christopher J. Larsen ,  David A. Daycock ,  Kunal Shrotri

IPC: H01L27/11521 ,  H01L29/788 ,  H01L29/423 ,  H01L21/308 ,  H01L27/11517 ,  H01L21/28 ,  H01L21/3213 ,  H01L27/11558 ,  H01L29/06 ,  H01L21/02

Abstract: Methods of forming semiconductor devices, memory cells, and arrays of memory cells include forming a liner on a conductive material and exposing the liner to a radical oxidation process to densify the liner. The densified liner may protect the conductive material from substantial degradation or damage during a subsequent patterning process. A semiconductor device structure, according to embodiments of the disclosure, includes features extending from a substrate and spaced by a trench exposing a portion of a substrate. A liner is disposed on sidewalls of a region of at least one conductive material in each feature. A semiconductor device, according to embodiments of the disclosure, includes memory cells, each comprising a control gate region and a capping region with substantially aligning sidewalls and a charge structure under the control gate region.

公开(公告)号：US20220254834A1

公开(公告)日：2022-08-11

申请号：US17171622

申请日：2021-02-09

Applicant: Micron Technology, Inc.

Inventor： David A. Daycock ,  Jonghun Kim

IPC: H01L27/24 ,  H01L45/00

Abstract: A method of forming an electronic device comprises forming a stack structure comprising vertically alternating insulative structures and additional insulative structures, and forming pillars comprising a channel material and at least one dielectric material vertically extending through the stack structure. The method comprises removing the additional insulative structures to form cell openings, forming a first conductive material within a portion of the cell openings, and forming a fill material adjacent to the first conductive material and within the cell openings. The fill material comprises sacrificial portions. The method comprises removing the sacrificial portions of the fill material, and forming a second conductive material within the cell openings in locations previously occupied by the sacrificial portions of the fill material. Related electronic devices, memory devices, and systems are also described.

公开(公告)号：US09153455B2

公开(公告)日：2015-10-06

申请号：US13921509

申请日：2013-06-19

Applicant: Micron Technology, Inc.

Inventor： Christopher J. Larsen ,  David A. Daycock ,  Kunal Shrotri

IPC: H01L29/788 ,  H01L21/308 ,  H01L21/28 ,  H01L27/115 ,  H01L29/423

CPC classification number: H01L29/42324 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/02337 ,  H01L21/28273 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/32139 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/0649 ,  H01L29/788

Abstract: Methods of forming semiconductor devices, memory cells, and arrays of memory cells include forming a liner on a conductive material and exposing the liner to a radical oxidation process to densify the liner. The densified liner may protect the conductive material from substantial degradation or damage during a subsequent patterning process. A semiconductor device structure, according to embodiments of the disclosure, includes features extending from a substrate and spaced by a trench exposing a portion of a substrate. A liner is disposed on sidewalls of a region of at least one conductive material in each feature. A semiconductor device, according to embodiments of the disclosure, includes memory cells, each comprising a control gate region and a capping region with substantially aligning sidewalls and a charge structure under the control gate region.

Abstract translation: 形成半导体器件，存储器单元和存储器单元阵列的方法包括在导电材料上形成衬垫并将衬套暴露于自由基氧化工艺以使衬垫致密化。 致密的衬垫可以保护导电材料在随后的图案化工艺期间免受实质的劣化或损坏。 根据本公开的实施例的半导体器件结构包括从衬底延伸并由暴露衬底的一部分的沟槽间隔开的特征。 衬垫设置在每个特征中的至少一个导电材料的区域的侧壁上。 根据本公开的实施例的半导体器件包括存储器单元，每个存储器单元包括控制栅极区域和具有基本对准侧壁的封盖区域和在控制栅极区域下方的电荷结构。

公开(公告)号：US20240407154A1

公开(公告)日：2024-12-05

申请号：US18677457

申请日：2024-05-29

Applicant: Micron Technology, Inc.

Inventor： Albert Daen Liao ,  Ting Zhao ,  Cheng Li ,  Ruijing Ge ,  Matthew Jacob Jerry ,  David A. Daycock ,  Kolya Yastrebenetsky ,  Kamal M. Karda

IPC: H10B12/00

Abstract: A variety of applications can include an apparatus having a memory device including digit lines isolated from each other by filling an area directly under the digit line with a dielectric material. The dielectric material can be any insulating material such as oxides or nitrides. The provision of the area directly under each digit line can be accomplished without etching out an entire layer of epitaxially grown regions for the memory cells vertically stacked in a three-dimensional array. In a three-dimensional DRAM, metal plates for capacitors can be isolated in a manner similar to the isolation of digit lines. Such processing can be scalable, which may allow for a three-dimensional DRAM to have hundreds memory cell tiers.