公开(公告)号：US20220384242A1

公开(公告)日：2022-12-01

申请号：US17818317

申请日：2022-08-08

Applicant: Micron Technology, Inc.

Inventor： Sidhartha Gupta ,  David Ross Economy ,  Richard J. Hill ,  Kyle A. Ritter ,  Naveen Kaushik

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/11582 ,  H01L27/11556

Abstract: A method of forming an apparatus includes forming pillar structures extending vertically through a first isolation material, forming conductive lines operatively coupled to the pillar structures, forming dielectric structures overlying the conductive lines, and forming air gaps between neighboring conductive lines. The air gaps are laterally adjacent to the conductive lines with a portion of the air gaps extending above a plane of an upper surface of the laterally adjacent conductive lines and a portion of the air gaps extending below a plane of a lower surface of the laterally adjacent conductive lines. Apparatuses, memory devices, methods of forming a memory device, and electronic systems are also disclosed.

公开(公告)号：US20220020662A1

公开(公告)日：2022-01-20

申请号：US17492185

申请日：2021-10-01

Applicant: Micron Technology, Inc.

Inventor： Pengyuan Zheng ,  David Ross Economy ,  Yongjun J. Hu ,  Kent H. Zhuang ,  Robert K. Grubbs

IPC: H01L23/373 ,  H01L23/535 ,  H01L21/768 ,  H01L21/02

Abstract: Methods, systems, and devices related to a memory device with a thermal barrier are described. The thermal barrier (e.g., a low density thermal barrier) may be positioned between an access line (e.g., a digit line or a word line) and a cell component. The thermal barrier may be formed on the surface of a barrier material by applying a plasma treatment to the barrier material. The thermal barrier may have a lower density than the barrier material and may be configured to thermally insulate the cell component from thermal energy generated in the memory device, among other benefits.

公开(公告)号：US20210202710A1

公开(公告)日：2021-07-01

申请号：US17180312

申请日：2021-02-19

Applicant: Micron Technology, Inc.

Inventor： David Ross Economy ,  Rita J. Klein ,  Jordan D. Greenlee ,  John Mark Meldrim ,  Brenda D. Kraus ,  Everett A. McTeer

IPC: H01L29/49 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11565

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and control gate levels. Channel material extends vertically along the stack. The control gate levels comprising conductive regions. The conductive regions include at least three different materials. Charge-storage regions are adjacent the control gate levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.

公开(公告)号：US20210183651A1

公开(公告)日：2021-06-17

申请号：US17101950

申请日：2020-11-23

Applicant: Micron Technology, Inc.

Inventor： David Ross Economy ,  Brian Beatty ,  John Mark Meldrim ,  Yongjun Jeff Hu ,  Jordan D. Greenlee

IPC: H01L21/02 ,  C01G41/00 ,  C23C16/28

Abstract: Described are methods for forming a multilayer conductive structure for semiconductor devices. A seed layer is formed comprising a metal and an additional constituent that in combination with the metal inhibits nucleation of a fill layer of the metal formed over the seed layer. Tungsten may be doped or alloyed with silicon to form the seed layer, with a tungsten fill being formed over the seed layer.

公开(公告)号：US10991425B2

公开(公告)日：2021-04-27

申请号：US16102494

申请日：2018-08-13

Applicant: Micron Technology, Inc.

Inventor： David Ross Economy ,  Stephen W. Russell

IPC: H01L47/00 ,  G11C13/00 ,  H01L45/00 ,  H01L27/24

Abstract: Methods, systems, and devices for access line grain modulation in a memory device are described. A memory cell stack in a cross-point memory array may be formed. In some examples, the memory cell stack may comprise a storage element. A barrier material may be formed above the memory cell stack. The barrier material may initially have an undulating top surface. In some cases, the top surface of the barrier material may be planarized. After the top surface of the barrier material is planarized, a metal layer for an access line may be formed on the top surface of the barrier material. Planarizing the top surface of the barrier material may impact the grain size of the metal layer. In some cases, planarizing the top surface of the barrier material may decrease the resistivity of access lines formed from the metal layer and thus increase current delivery throughout the memory device.

公开(公告)号：US20200211843A1

公开(公告)日：2020-07-02

申请号：US16235765

申请日：2018-12-28

Applicant: Micron Technology, Inc.

Inventor： David Ross Economy ,  Brian Beatty ,  John Mark Meldrim ,  Yongjun Jeff Hu ,  Jordan D. Greenlee

IPC: H01L21/02 ,  C23C16/28 ,  C01G41/00

Abstract: Described are methods for forming a multilayer conductive structure for semiconductor devices. A seed layer is formed comprising a metal and an additional constituent that in combination with the metal inhibits nucleation of a fill layer of the metal formed over the seed layer. Tungsten may be doped or alloyed with silicon to form the seed layer, with a tungsten fill being formed over the seed layer.

公开(公告)号：US10700091B2

公开(公告)日：2020-06-30

申请号：US16431527

申请日：2019-06-04

Applicant: Micron Technology, Inc.

Inventor： David Ross Economy ,  John Mark Meldrim ,  Haoyu Li ,  Yongjun Jeff Hu ,  Christopher W. Petz ,  Daniel Billingsley ,  Everett A. McTeer

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L21/311 ,  H01L27/11565 ,  H01L21/768 ,  H01L27/1157

Abstract: Some embodiments include an assembly which has channel material pillars, and which has memory cells along the channel material pillars. A conductive structure is under the channel material pillars. The conductive structure has doped semiconductor material in direct contact with bottom regions of the channel material pillars. One or more of magnesium, scandium, yttrium and lanthanide elements is along the bottom regions of the channel material pillars. Some embodiments include methods of forming assemblies. A structure is formed, and a mass is formed against an upper surface of the structure. Plugs are formed within openings in the mass. The plugs comprise a second material over a first material. The first material includes one or more of magnesium, scandium, yttrium and lanthanide elements. Openings are formed to terminate on the first material, and are then extended through the first material. Channel material pillars are formed within the openings.

公开(公告)号：US20200051624A1

公开(公告)日：2020-02-13

申请号：US16102494

申请日：2018-08-13

Applicant: Micron Technology, Inc.

Inventor： David Ross Economy ,  Stephen W. Russell

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

Abstract: Methods, systems, and devices for access line grain modulation in a memory device are described. A memory cell stack in a cross-point memory array may be formed. In some examples, the memory cell stack may comprise a storage element. A barrier material may be formed above the memory cell stack. The barrier material may initially have an undulating top surface. In some cases, the top surface of the barrier material may be planarized. After the top surface of the barrier material is planarized, a metal layer for an access line may be formed on the top surface of the barrier material. Planarizing the top surface of the barrier material may impact the grain size of the metal layer. In some cases, planarizing the top surface of the barrier material may decrease the resistivity of access lines formed from the metal layer and thus increase current delivery throughout the memory device.

公开(公告)号：US10355014B1

公开(公告)日：2019-07-16

申请号：US15852989

申请日：2017-12-22

Applicant: Micron Technology, Inc.

Inventor： David Ross Economy ,  John Mark Meldrim ,  Haoyu Li ,  Yongjun Jeff Hu ,  Christopher W. Petz ,  Daniel Billingsley ,  Everett A. McTeer

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L21/311 ,  H01L27/11565 ,  H01L21/768

Abstract: Some embodiments include an assembly which has channel material pillars, and which has memory cells along the channel material pillars. A conductive structure is under the channel material pillars. The conductive structure has doped semiconductor material in direct contact with bottom regions of the channel material pillars. One or more of magnesium, scandium, yttrium and lanthanide elements is along the bottom regions of the channel material pillars. Some embodiments include methods of forming assemblies. A structure is formed, and a mass is formed against an upper surface of the structure. Plugs are formed within openings in the mass. The plugs comprise a second material over a first material. The first material includes one or more of magnesium, scandium, yttrium and lanthanide elements. Openings are formed to terminate on the first material, and are then extended through the first material. Channel material pillars are formed within the openings.

公开(公告)号：US12022666B2

公开(公告)日：2024-06-25

申请号：US17534953

申请日：2021-11-24

Applicant: Micron Technology, Inc.

Inventor： David Ross Economy ,  Andrew Leslie Beemer

IPC: H10B63/00 ,  H01L21/321 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/80 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53266 ,  H10N70/231 ,  H10N70/826 ,  H10N70/841 ,  H10N70/882

Abstract: Methods, systems, and devices for via formation in a memory device are described. A memory cell stack for a memory array may be formed. In some examples, the memory cell stack may comprise a storage element. A via may also be formed in an area outside of the memory array, and the via may protrude from a material that surrounds the via. A material may then be formed above the memory cell stack and also above the via, and the top surface of the barrier material may be planarized until at least a portion of the via is exposed. A subsequently formed material may thereby be in direct contact with the top of the via, while a portion of the initially formed material may remain above the memory cell stack.