公开(公告)号：US12250812B2

公开(公告)日：2025-03-11

申请号：US18094906

申请日：2023-01-09

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Nancy M. Lomeli ,  John D. Hopkins ,  Jiewei Chen ,  Indra V. Chary ,  Jun Fang ,  Vladimir Samara ,  Kaiming Luo ,  Rita J. Klein ,  Xiao Li ,  Vinayak Shamanna

IPC: H01L21/306 ,  G11C5/02 ,  G11C5/06 ,  G11C16/04 ,  H10B41/27 ,  H10B43/27 ,  H10B43/30

Abstract: Some embodiments include an integrated assembly having a source structure, and having a stack of alternating conductive levels and insulative levels over the source structure. Cell-material-pillars pass through the stack. The cell-material-pillars are arranged within a configuration which includes a first memory-block-region and a second memory-block-region. The cell-material-pillars include channel material which is electrically coupled with the source structure. Memory cells are along the conductive levels and include regions of the cell-material-pillars. A panel is between the first and second memory-block-regions. The panel has a first material configured as a container shape. The container shape defines opposing sides and a bottom of a cavity. The panel has a second material within the cavity. The second material is compositionally different from the first material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20240071495A1

公开(公告)日：2024-02-29

申请号：US17896775

申请日：2022-08-26

Applicant: Micron Technology, Inc.

Inventor： Jiewei Chen ,  Jordan D. Greenlee ,  Shuangqiang Luo ,  Silvia Borsari

IPC: G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: Memory circuitry comprising strings of memory cells comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers extend from the memory-array region into a stair-step region. The stair-step region comprises a cavity comprising a flight of stairs having insulative material atop treads of the stairs. Individual of the treads comprise conducting material of one of the conductive tiers. Conductive vias extend through the insulative material. Individual of the conductive vias are directly above and directly against the conducting material of the respective individual tread. A lining is over sidewalls of the individual conductive vias. The lining has a bottom. The individual conductive vias are directly under the bottom of the lining directly above the conducting material of the respective individual tread. Other embodiments, including method, are disclosed.

公开(公告)号：US11895834B2

公开(公告)日：2024-02-06

申请号：US17674478

申请日：2022-02-17

Applicant: Micron Technology, Inc.

Inventor： Jiewei Chen ,  Jordan D. Greenlee ,  Mithun Kumar Ramasahayam ,  Nancy M. Lomeli

IPC: H10B41/10 ,  G11C16/04 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B41/35 ,  H10B43/35

CPC classification number: H10B41/10 ,  G11C16/0483 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B41/35 ,  H10B43/35

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings extend through the insulative tiers and the conductive tiers. Horizontally-elongated trenches are between immediately-laterally-adjacent of the memory blocks. Conductor material is in and extends elevationally along sidewalls of the trenches laterally-over the conductive tiers and the insulative tiers and directly electrically couples together conducting material of individual of the conductive tiers. The conductor material is exposed to oxidizing conditions to form an insulative oxide laterally-through the conductor material laterally-over individual of the insulative tiers to separate the conducting material of the individual conductive tiers from being directly electrically coupled together by the conductor material. Additional embodiments are disclosed.

公开(公告)号：US20230395510A1

公开(公告)日：2023-12-07

申请号：US17812141

申请日：2022-07-12

Applicant: Micron Technology, Inc.

Inventor： Mithun Kumar Ramasahayam ,  Jordan D. Greenlee ,  Harsh Narendrakumar Jain ,  Jiewei Chen ,  Indra V. Chary

IPC: H01L23/535 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53242 ,  H01L23/53257 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76888

Abstract: Microelectronic devices include a stack with a vertically alternating sequence of insulative and conductive structures arranged in tiers. A staircased stadium within the stack comprises steps at different tier elevations of a group of the tiers. Treads of the steps are each provided by an upper surface area of one of the conductive structures within the group of the tiers and by an upper surface area of a metal oxide region extending through the one of the conductive structures. A pair of conductive contact structures extends to one of the steps. A first conductive contact structure of the pair terminates at the tread of the step, within the area of the conductive structure. A second conductive contact structure of the pair extends through the tread of the step, within the upper surface area of the metal oxide region. Related fabrication methods and electronic systems are also disclosed.

公开(公告)号：US20230389313A1

公开(公告)日：2023-11-30

申请号：US17869586

申请日：2022-07-20

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Jiewei Chen ,  John D. Hopkins ,  Everett A. McTeer

IPC: H01L27/11582 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L27/11556

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a first vertical stack comprising vertically-alternating insulative tiers and conductive tiers. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. A second vertical stack is aside the first vertical stack. The second vertical stack comprises insulative tiers collectively comprising at least two different compositions relative individual of the insulative tiers. Individual of the at least two different compositions comprise silicon nitride. One of the individual different compositions comprise carbon-doped silicon nitride having at least 0.5 atomic percent more carbon than atomic percent of carbon, if any, in the silicon nitride of another of the individual different compositions. Other embodiments, including method, are disclosed.

公开(公告)号：US20230209819A1

公开(公告)日：2023-06-29

申请号：US17655222

申请日：2022-03-17

Applicant: Micron Technology, Inc.

Inventor： Nancy M. Lomeli ,  Jiewei Chen ,  Naiming Liu

IPC: H01L27/11556 ,  G11C5/02 ,  H01L27/11582 ,  G11C5/06 ,  H01L23/538

CPC classification number: H01L27/11556 ,  G11C5/025 ,  H01L27/11582 ,  G11C5/06 ,  H01L23/5386

Abstract: A microelectronic device includes a stack structure including insulative structures and conductive structures vertically alternating with the insulative structures. At least one of the insulative structures includes interfacial regions proximate interfaces between the at least one of the insulative structures and two of the conductive structures vertically neighboring the at least one of the insulative structures; and an intermediate region interposed between the interfacial regions. The intermediate region has a different material composition and relatively greater strength than the interfacial regions.

公开(公告)号：US12272421B2

公开(公告)日：2025-04-08

申请号：US17895959

申请日：2022-08-25

Applicant: Micron Technology, Inc.

Inventor： Jiewei Chen ,  Mithun Kumar Ramasahayam ,  Tomoko Ogura Iwasaki

IPC: G11C7/10

Abstract: A system for manufacturing a memory device forms a memory array comprising a plurality of memory cells arranged in a plurality of memory strings along a plurality of memory array pillars and forms a logic layer disposed above the memory array, the logic layer comprising a plurality of latches arranged along a plurality of logic layer latch pillars, the plurality of latches to store a multi-bit data pattern representing a sequence of bits to be programmed to the plurality of memory cells of the memory array.

公开(公告)号：US20250098126A1

公开(公告)日：2025-03-20

申请号：US18967278

申请日：2024-12-03

Applicant: Micron Technology, Inc.

Inventor： Tracy D. Evans ,  Gloria Y. Yang ,  Jiewei Chen ,  Jing Zhou

IPC: H05K7/20 ,  G05B15/02

Abstract: Systems associated with device temperature adjustment are described. A device temperature adjustment system can include an electronic device having a temperature sensor integrated therein to detect a temperature of the electronic device and a temperature adjust module coupled to the electronic device to adjust a temperature of the electronic device based on the detected temperature.

公开(公告)号：US20240081076A1

公开(公告)日：2024-03-07

申请号：US17929911

申请日：2022-09-06

Applicant: Micron Technology, Inc.

Inventor： Sidhartha Gupta ,  Matthew J. King ,  Jiewei Chen ,  Yi Hu

IPC: H01L27/11575 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L27/11575 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11582

Abstract: An electronic device comprises a stack comprising tiers of alternating conductive structures and insulative structures adjacent to a source, and strings of memory cells extending vertically through the stack. The strings of memory cells individually comprising a channel material extending vertically through the stack. The electronic device comprises an additional stack adjacent to the stack and comprising tiers of alternating additional conductive structures and additional insulative structures, pillars extending through the additional stack and adjacent to the strings of memory cells, conductive contacts adjacent to the pillars, and isolation structures laterally intervening between neighboring pillars. The isolation structures exhibit a weave pattern, and portions of the isolation structures are laterally adjacent to and physically contact the conductive contacts. Related memory devices, systems, and methods are also described.

公开(公告)号：US20240071505A1

公开(公告)日：2024-02-29

申请号：US18237815

申请日：2023-08-24

Applicant: Micron Technology, Inc.

Inventor： Jiewei Chen ,  Mithun Kumar Ramasahayam ,  Tomoko Ogura Iwasaki ,  June Lee ,  Luyen Vu

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3459

Abstract: Control logic in a memory device causes a pass voltage to be applied to a plurality of wordlines of a block of a memory array of the memory device, the block comprising a plurality of sub-blocks, and the pass voltage to boost a channel potential of each of the plurality of sub-blocks to a boost voltage. The control logic further selectively discharges the boost voltage from one or more of the plurality of sub-blocks according to a data pattern representing a sequence of bits to be programmed to respective memory cells of the plurality of sub-blocks. In addition, the control logic causes a single programming pulse to be applied to a selected wordline of the plurality of wordlines of the block to program the respective memory cells of the plurality of sub-blocks according to the data pattern.