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    Compositions of Matter, and Methods of Removing Silicon Dioxide
    11.
    发明申请
    Compositions of Matter, and Methods of Removing Silicon Dioxide 有权
    物质组成和去除二氧化硅的方法

    公开(公告)号：US20140037527A1

    公开(公告)日：2014-02-06

    申请号：US14046832

    申请日：2013-10-04

    Applicant: Micron Technology, Inc.

    Inventor： Nishant Sinha

    IPC: H01L21/308

    CPC classification number: H01L21/3081 ,  H01L21/31111

    Abstract: Some embodiments include methods of removing silicon dioxide in which the silicon dioxide is exposed to a mixture that includes activated hydrogen and at least one primary, secondary, tertiary or quaternary ammonium halide. The mixture may also include one or more of thallium, BX3 and PQ3, where X and Q are halides. Some embodiments include methods of selectively etching undoped silicon dioxide relative to doped silicon dioxide, in which thallium is incorporated into the doped silicon dioxide prior to the etching. Some embodiments include compositions of matter containing silicon dioxide doped with thallium to a concentration of from about 1 weight % to about 10 weight %.

    Abstract translation: 一些实施方案包括去除其中二氧化硅暴露于包括活性氢和至少一种伯，仲，叔或季铵卤化物的混合物的二氧化硅的方法。 混合物还可以包括铊，BX 3和PQ 3中的一种或多种，​​其中X和Q是卤化物。 一些实施方案包括相对于掺杂二氧化硅选择性地蚀刻未掺杂二氧化硅的方法，其中在蚀刻之前将铊掺入掺杂的二氧化硅中。 一些实施方案包括含有掺杂铊的二氧化硅至约1重量％至约10重量％的浓度的物质的组合物。

    Semiconductor devices comprising silver
    12.
    发明授权
    Semiconductor devices comprising silver 有权

    公开(公告)号：US10862030B2

    公开(公告)日：2020-12-08

    申请号：US16538477

    申请日：2019-08-12

    Applicant: Micron Technology, Inc.

    Inventor： Sanh D. Tang ,  Scott E. Sills ,  Whitney L. West ,  Rob B. Goodwin ,  Nishant Sinha

    IPC: H01L45/00 ,  H01L21/768 ,  H01L23/532

    Abstract: Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. An annealing process may be performed to form a mixture or an alloy of the silver and the first conductive material. The methods enable formation of silver-containing conductive elements having reduced dimensions (e.g., less than about 20 nm). The resulting conductive elements have a desirable resistivity. The methods may be used, for example, to form interconnects for electrically connecting active devices and to form electrodes for memory cells. A semiconductor structure and a memory cell including such a conductive structure are also disclosed.

    MULTI-TIERED SEMICONDUCTOR DEVICES AND ASSOCIATED METHODS
    15.
    发明申请
    MULTI-TIERED SEMICONDUCTOR DEVICES AND ASSOCIATED METHODS 有权
    多层半导体器件及相关方法

    公开(公告)号：US20160020218A1

    公开(公告)日：2016-01-21

    申请号：US14867914

    申请日：2015-09-28

    Applicant: Micron Technology, Inc.

    Inventor： Nishant Sinha

    IPC: H01L27/115 ,  H01L29/786 ,  H01L29/788

    CPC classification number: H01L27/11556 ,  H01L21/31111 ,  H01L21/31144 ,  H01L27/0688 ,  H01L29/78642 ,  H01L29/7889

    Abstract: Methods of fabricating multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, a first dielectric is formed, and a second dielectric is formed in contact with the first dielectric. A channel is formed through the first dielectric and the second dielectric with a first etch chemistry, a void is formed in the first dielectric with a second etch chemistry, and a device is formed at least partially in the void in the first dielectric. Additional embodiments are also described.

    Abstract translation: 描述制造多层半导体器件的方法以及包括它们的装置和系统。 在一种这样的方法中，形成第一电介质，并且形成与第一电介质接触的第二电介质。 通过第一电介质和第二电介质通过第一蚀刻化学品形成通道，在第一电介质中用第二蚀刻化学物质形成空隙，并且器件至少部分地形成在第一电介质的空隙中。 还描述了另外的实施例。

    Wet etchants including at least one fluorosurfactant etch blocker
    17.
    发明授权
    Wet etchants including at least one fluorosurfactant etch blocker 有权
    湿蚀刻剂包括至少一种含氟表面活性剂蚀刻阻挡剂

    公开(公告)号：US09175217B2

    公开(公告)日：2015-11-03

    申请号：US14253005

    申请日：2014-04-15

    Applicant: Micron Technology, Inc.

    Inventor： Nishant Sinha ,  J. Neil Greeley

    IPC: C11D1/02 ,  C11D1/83 ,  C11D7/28 ,  C11D7/30 ,  C09K13/08 ,  H01L21/3105 ,  H01L21/311 ,  C09K13/06

    CPC classification number: C09K13/08 ,  C09K13/06 ,  H01L21/31055 ,  H01L21/31111

    Abstract: Methods for preventing isotropic removal of materials at corners faulted by seams, keyholes, and other anomalies in films or other structures include use of etch blockers to cover or coat such corners. This covering or coating prevents exposure of the corners to isotropic etch solutions and cleaning solutions and, thus, prevents higher material removal rates at the corners than at smoother areas of the structure or film. Solutions, including wet etchants and cleaning solutions, that include at least one type of etch blocker are also disclosed, as are systems for preventing higher rates of material removal at corners formed by seams, crevices, or recesses in a film or other structure. Semiconductor device structures in which etch blockers are located so as to prevent isotropic etchants from removing material from corners of seams, crevices, or recesses of a film or other structure at undesirably high rates are also disclosed.

    Abstract translation: 在膜或其他结构中的接缝，键孔和其它异常现象的角落处的材料的各向同性去除方法包括使用蚀刻阻挡剂来覆盖或涂覆这些角。 这种覆盖物或涂层防止角部暴露于各向同性蚀刻溶液和清洁溶液，并且因此防止在角部比在结构或膜的平滑区域更高的材料去除速率。 还公开了包括至少一种类型的蚀刻阻挡剂的解决方案，包括湿蚀刻剂和清洁溶液，以及用于防止在膜或其它结构中由接缝，缝隙或凹陷形成的拐角处更高速率的材料去除的系统。 还公开了其中蚀刻阻挡剂被定位以防止各向同性蚀刻剂从不期望的高速率的接缝，裂缝或膜或其它结构的凹陷的角落移除材料的半导体器件结构。

    Methods of Processing Substrates and Methods of Forming Conductive Connections to Substrates
    19.
    发明申请
    Methods of Processing Substrates and Methods of Forming Conductive Connections to Substrates 有权
    基板的加工方法与基材的导电连接方法

    公开(公告)号：US20140248769A1

    公开(公告)日：2014-09-04

    申请号：US14258885

    申请日：2014-04-22

    Applicant: Micron Technology, Inc.

    Inventor： Nishant Sinha ,  Gurtej S. Sandhu

    IPC: H01L21/768

    CPC classification number: H01L21/76879 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76867

    Abstract: Embodiments disclosed include methods of processing substrates, including methods of forming conductive connections to substrates. In one embodiment, a method of processing a substrate includes forming a material to be etched over a first material of a substrate. The material to be etched and the first material are of different compositions. The material to be etched is etched in a dry etch chamber to expose the first material. After the etching, the first material is contacted with a non-oxygen-containing gas in situ within the dry etch chamber effective to form a second material physically contacting onto the first material. The second material comprises a component of the first material and a component of the gas. In one embodiment, the first material is contacted with a gas that may or may not include oxygen in situ within the dry etch chamber effective to form a conductive second material.

    Abstract translation: 公开的实施例包括处理衬底的方法，包括形成与衬底的导电连接的方法。 在一个实施例中，处理衬底的方法包括在衬底的第一材料上形成待蚀刻的材料。 待蚀刻的材料和第一种材料具有不同的组成。 待蚀刻的材料在干蚀刻室中蚀刻以暴露第一材料。 在蚀刻之后，第一材料在干蚀刻室内原位与非含氧气体接触，有效地形成物理接触第一材料的第二材料。 第二材料包括第一材料的组分和气体的组分。 在一个实施方案中，第一材料与干蚀刻室内可能或可能不包含氧原位的气体接触，有效地形成导电的第二材料。

    APPARATUS FOR PARTICLE REMOVAL
    20.
    发明申请
    APPARATUS FOR PARTICLE REMOVAL 审中-公开
    装置去除颗粒

    公开(公告)号：US20140102903A1

    公开(公告)日：2014-04-17

    申请号：US14107449

    申请日：2013-12-16

    Applicant: Micron Technology, Inc.

    Inventor： Nishant Sinha

    IPC: H01L21/67

    CPC classification number: H01L21/67057 ,  B08B3/04 ,  B08B7/00 ,  H01L21/67086 ,  Y10T137/206 ,  Y10T428/24521

    Abstract: Methods and apparatus for cleaning a substrate (e.g., wafer) in the fabrication of semiconductor devices utilizing electrorheological (ER) and magnetorheological (MR) fluids to remove contaminant residual particles from a surface of the substrate are provided.

    Abstract translation: 提供了利用电流变学（ER）和磁流变（MR）流体制造半导体器件中的衬底（例如晶片）以从衬底的表面去除污染物残留颗粒的方法和装置。

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