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    ERROR CONTROL FOR MEMORY DEVICE
    11.
    发明申请
    ERROR CONTROL FOR MEMORY DEVICE 有权

    公开(公告)号：US20220310189A1

    公开(公告)日：2022-09-29

    申请号：US17730973

    申请日：2022-04-27

    Applicant: Micron Technology, Inc.

    Inventor： Nobuo Yamamoto ,  Donald Martin Morgan ,  Victor Wong ,  Jongtae Kwak

    IPC: G11C29/42 ,  G11C29/44 ,  G11C16/10 ,  G11C16/26 ,  G11C29/20

    Abstract: Methods, systems, and devices for error control for memory device are described. A memory device may be configured to perform memory management operations including error control operations. For example, a memory device may be configured to perform an error control operation on data stored in a first memory cell coupled with a source row of a memory array. The memory device may be configured to write the data to a second memory cell coupled with the target row of the memory array based on performing the error control operation on the data and determine whether the management operation is complete based at least in part on the first column address of the first memory cell. The memory device may also generate an output signal to perform the error control operation on a third memory cell coupled with the source row based on determining whether the management operation is complete.

    Error control for memory device
    12.
    发明授权
    Error control for memory device 有权

    公开(公告)号：US11322218B2

    公开(公告)日：2022-05-03

    申请号：US16895960

    申请日：2020-06-08

    Applicant: Micron Technology, Inc.

    Inventor： Nobuo Yamamoto ,  Donald Martin Morgan ,  Victor Wong ,  Jongtae Kwak

    IPC: G11C29/00 ,  G11C29/42 ,  G11C29/44 ,  G11C16/10 ,  G11C16/26 ,  G11C29/20

    Abstract: Methods, systems, and devices for error control for memory device are described. A memory device may be configured to perform memory management operations including error control operations. For example, a memory device may be configured to perform an error control operation on data stored in a first memory cell coupled with a source row of a memory array. The memory device may be configured to write the data to a second memory cell coupled with the target row of the memory array based on performing the error control operation on the data and determine whether the management operation is complete based at least in part on the first column address of the first memory cell. The memory device may also generate an output signal to perform the error control operation on a third memory cell coupled with the source row based on determining whether the management operation is complete.

    Temperature-based access timing for a memory device
    13.
    发明授权
    Temperature-based access timing for a memory device 有权

    公开(公告)号：US10978130B1

    公开(公告)日：2021-04-13

    申请号：US16829996

    申请日：2020-03-25

    Applicant: Micron Technology, Inc.

    Inventor： Victor Wong ,  Sihong Kim ,  Hiroshi Akamatsu ,  Daniele Vimercati ,  John D. Porter

    IPC: G11C7/04 ,  G11C11/22

    Abstract: Methods, systems, and devices for temperature-based access timing for a memory device are described. In some memory devices, accessing memory cells may be associated with different operations that are variously dependent on a temperature of the memory device. For example, some operations associated with accessing a memory cell may have a longer duration and others a shorter duration depending on the temperature of the memory device. In accordance with examples as disclosed herein, a memory device may be configured for performing some portions of an access operation according to a duration that is proportional to a temperature of the memory device, and performing other portions of the access operation according to a duration that is inversely proportional to a temperature of the memory device.

    Apparatuses and methods for implementing masked write commands
    16.
    发明授权
    Apparatuses and methods for implementing masked write commands 有权
    用于实现屏蔽写入命令的设备和方法

    公开(公告)号：US09508409B2

    公开(公告)日：2016-11-29

    申请号：US14254378

    申请日：2014-04-16

    Applicant: Micron Technology, Inc.

    Inventor： Mark K. Hadrick ,  Jeffrey P. Wright ,  Victor Wong ,  Simon J. Lovett ,  Donald M. Morgan ,  William F. Jones ,  Sujeet Ayyapureddi ,  Dean D. Gans ,  Jongtae Kwak

    IPC: G11C7/22 ,  G11C7/10 ,  G11C8/12

    CPC classification number: G11C7/22 ,  G11C7/1009 ,  G11C7/1042 ,  G11C8/12 ,  G11C2207/229

    Abstract: Apparatuses and methods for implementing masked write commands are disclosed herein. An example apparatus may include a memory bank, a local buffer circuit, and an address control circuit. The local buffer circuit may be associated with the memory bank. The address control circuit may be coupled to the memory bank and configured to receive a command and an address associated with the command. The address control circuit may include a global buffer circuit configured to store the address. The address control circuit may further be configured to delay the command using one of a plurality of command paths based, at least in part, on a write latency and to provide the address stored in the global buffer circuit to the local buffer circuit to be stored therein.

    Abstract translation: 本文公开了用于实现屏蔽写入命令的装置和方法。 示例性装置可以包括存储体，局部缓冲电路和地址控制电路。 本地缓冲电路可以与存储体相关联。 地址控制电路可以耦合到存储体并被配置为接收命令和与该命令相关联的地址。 地址控制电路可以包括被配置为存储地址的全局缓冲电路。 地址控制电路还可以被配置为至少部分地基于写等待时间来延迟使用多个命令路径之一的命令，并且将存储在全局缓冲器电路中的地址提供给要存储的本地缓冲器电路 其中。

    System and method for processing signals in high speed DRAM
    17.
    发明授权
    System and method for processing signals in high speed DRAM 有权
    用于处理高速DRAM信号的系统和方法

    公开(公告)号：US08755247B2

    公开(公告)日：2014-06-17

    申请号：US13886096

    申请日：2013-05-02

    Applicant: Micron Technology, Inc.

    Inventor： Ben Ba ,  Victor Wong

    IPC: G11C11/00

    CPC classification number: G11C8/08 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C8/12 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4087

    Abstract: The embodiments described herein provide memory devices. In one embodiment, a memory device includes bank control logic configured to generate a modified bank address signal and an active driver configured to provide a bank activate signal, receive an activate command signal, execute an activate command of the activate command signal at each one of a group of clock cycles, in which each one of the group of clock cycles is greater than one clock cycle, and receive the modified bank address signal, in which the modified bank address signal is high for at least a portion of each one of the group of clock cycles and the at least a portion of each one of the group of clock cycles is greater than one clock cycle.

    Abstract translation: 这里描述的实施例提供存储器件。 在一个实施例中，存储器设备包括：组控制逻辑，其被配置为生成修改的存储体地址信号;以及主动驱动器，其被配置为提供存储体激活信号，接收激活命令信号，执行激活命令信号的激活命令 一组时钟周期，其中该组时钟周期中的每一个大于一个时钟周期，并且接收修改的库地址信号，其中修改的库地址信号对于每个时钟周期的每一个的至少一部分 一组时钟周期，并且该组时钟周期中的每一个的至少一部分大于一个时钟周期。

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