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公开(公告)号：US20150243351A1
公开(公告)日：2015-08-27
申请号：US14707684
申请日：2015-05-08
Applicant: Micron Technology, Inc.
Inventor： Violante Moschiano , Tommaso Vali , Giovanni Naso , Vishal Sarin , William Henry Radke , Theodore T. Pekny
IPC: G11C11/56
CPC classification number: G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/24 , G11C16/26 , G11C16/3418 , G11C16/3427 , G11C2211/5641
Abstract: Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed “aggressor” memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation.
Abstract translation: 电荷存储存储器中的阈值电压由阈值电压放置来控制，例如提供更可靠的操作并减少诸如相邻电荷存储元件和寄生耦合的因素的影响。 相邻编程的“侵略者”存储器单元的阈值电压的预补偿或后补偿降低了闪存系统中的阈值电压不确定性。 使用具有诸如查找表之类的数据结构的缓冲器提供了可编程的阈值电压分布，使得能够定制多级单元闪存中的数据状态的分布，例如提供更可靠的操作。
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公开(公告)号：US20130083605A1
公开(公告)日：2013-04-04
申请号：US13686488
申请日：2012-11-27
Applicant: Micron Technology, Inc.
Inventor： William Henry Radke
IPC: G11C16/26
CPC classification number: G11C16/26 , G11C7/1021 , G11C16/04 , G11C16/3418 , G11C29/025 , G11C29/44 , G11C29/50
Abstract: A memory device is described that provides increased output data to help evaluate data errors from bit line coupling and floating gate coupling during a read operation. Multiple rows, or pages, of data are read to allow an internal or external decoder to evaluate memory cell data.
Abstract translation: 描述了一种存储器件，其提供增加的输出数据以帮助在读取操作期间从位线耦合和浮动栅极耦合评估数据错误。 读取多行或多页数据以允许内部或外部解码器评估存储器单元数据。
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公开(公告)号：US09983928B2
公开(公告)日：2018-05-29
申请号：US15148321
申请日：2016-05-06
Applicant: Micron Technology, Inc.
Inventor： William Henry Radke
CPC classification number: G06F11/1068 , G06F11/1016 , G06F11/1048 , G06F11/1072 , G11C29/52 , H03M13/116 , H03M13/2906 , H03M13/356
Abstract: Some embodiments include apparatuses and methods having first memory cells, a first access line configured to access the first memory cells, second memory cells, and a second access line configured to access the second memory cells. One of such apparatuses can include a controller configured to cause data to be stored in a memory portion of the first memory cells, to cause a first portion of an error correction code associated with the data to be stored in another memory portion of the first memory cells, and to cause a second portion of the error correction code to be stored in the second memory cells. Other embodiments including additional apparatuses and methods are described.
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公开(公告)号：US20150325309A1
公开(公告)日：2015-11-12
申请号：US14803918
申请日：2015-07-20
Applicant: Micron Technology, Inc.
Inventor： Violante Moschiano , Tommaso Vali , Giovanni Naso , Vishal Sarin , William Henry Radke , Theodore T. Pekny
CPC classification number: G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/24 , G11C16/26 , G11C16/3418 , G11C16/3427 , G11C2211/5641
Abstract: Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed aggressor memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation. Additional apparatus, systems, and methods are provided.
Abstract translation: 电荷存储存储器中的阈值电压由阈值电压放置来控制，例如提供更可靠的操作并减少诸如相邻电荷存储元件和寄生耦合的因素的影响。 对于相邻编程的侵略存储器单元的阈值电压的预补偿或后补偿降低了闪存系统中的阈值电压不确定性。 使用具有诸如查找表之类的数据结构的缓冲器提供了可编程的阈值电压分布，使得能够定制多级单元闪存中的数据状态的分布，例如提供更可靠的操作。 提供附加的装置，系统和方法。
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公开(公告)号：US08713385B2
公开(公告)日：2014-04-29
申请号：US13741148
申请日：2013-01-14
Applicant: Micron Technology, Inc.
Inventor： William Henry Radke , Peter Sean Feeley , Siamack Nemazie
IPC: G11C29/00
CPC classification number: G06F11/006 , G06F11/106
Abstract: Various embodiments include methods, apparatus, and systems to scan at least a portion of a memory device for potential errors when a condition for scanning is met. The condition may be dependent on one or more of a number of read operations, a number of write operations, time, and others. Other embodiments including additional methods, apparatus, and systems are disclosed.
Abstract translation: 各种实施例包括当满足扫描条件时扫描存储器件的至少一部分以用于潜在错误的方法，装置和系统。 条件可以取决于多个读取操作，多个写入操作，时间等中的一个或多个。 公开了包括附加方法，装置和系统的其它实施例。
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Patent Agency Ranking
公开(公告)号：US20130254630A1
公开(公告)日：2013-09-26
申请号：US13904331
申请日：2013-05-29
Applicant: Micron Technology, Inc.
Inventor： Michael Murray , William Henry Radke
IPC: G06F11/10
CPC classification number: G06F11/1008 , G06F11/1072 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C29/00 , G11C2211/5642
Abstract: Methods, apparatus, systems, and data structures may operate to combine block management data with a portion of data, to generate error correction data for the combined portion, and to store the data, the block management data, the error correction data for the combined portion, and error correction data for the data in a memory. Additional embodiments may operate to generate or store error correction data for each of a plurality of sectors of a page except for a particular sector in the page and combine block management data with the particular sector to generate a modified sector. Additional embodiments may operate to generate or store error correction data for the modified sector and combine the plurality of sectors, the error correction data for each of the plurality of sectors other than the particular page, and the block management data and the error correction data for the modified sector.
Abstract translation: 方法，装置，系统和数据结构可以操作以将块管理数据与数据的一部分组合，以产生组合部分的纠错数据，并存储数据，块管理数据，组合的纠错数据 部分和用于存储器中的数据的纠错数据。 另外的实施例可以操作以生成或存储除了页面中的特定扇区之外的页面的多个扇区中的每一个的纠错数据，并且将块管理数据与特定扇区组合以生成修改的扇区。 另外的实施例可以操作以产生或存储修改的扇区的纠错数据，并组合多个扇区，除了特定页面之外的多个扇区中的每一个的纠错数据以及块管理数据和用于 修改部门。
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公开(公告)号：US20130132802A1
公开(公告)日：2013-05-23
申请号：US13746189
申请日：2013-01-21
Applicant: Micron Technology, Inc.
Inventor： William Henry Radke
IPC: H03M13/05
CPC classification number: H03M13/05 , G06F11/1008 , G06F11/1012 , G06F11/1072 , G11C29/00
Abstract: Memory devices and methods are described such as those that mix data and associated error correction code blocks between multiple memory device locations. Examples include mixing between multiple memory blocks, mixing between memory pages, mixing between memory chips and mixing between memory modules. In selected examples, memory blocks and associated error correction code are mixed between multiple levels of memory device hierarchy.
Abstract translation: 描述存储器件和方法，例如在多个存储器件位置之间混合数据和相关联的纠错码块的存储器件和方法。 示例包括在多个存储器块之间进行混合，在存储器页之间进行混合，存储器芯片之间的混合以及存储器模块之间 在所选择的示例中，存储器块和相关联的纠错码在多级存储器件层级之间混合。
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公开(公告)号：US20150135037A1
公开(公告)日：2015-05-14
申请号：US14600800
申请日：2015-01-20
Applicant: Micron Technology, Inc.
Inventor： William Henry Radke
IPC: G06F11/10
CPC classification number: G06F11/1068 , G06F11/1016 , G06F11/1048 , G06F11/1072 , G11C29/52 , H03M13/116 , H03M13/2906 , H03M13/356
Abstract: Some embodiments include apparatuses and methods having first memory cells, a first access line configured to access the first memory cells, second memory cells, and a second access line configured to access the second memory cells. One of such apparatuses can include a controller configured to cause data to be stored in a memory portion of the first memory cells, to cause a first portion of an error correction code associated with the data to be stored in another memory portion of the first memory cells, and to cause a second portion of the error correction code to be stored in the second memory cells. Other embodiments including additional apparatuses and methods are described.
Abstract translation: 一些实施例包括具有第一存储器单元的装置和方法，被配置为访问第一存储器单元的第一访问线，第二存储器单元以及被配置为访问第二存储单元的第二访问线。 这种设备之一可以包括控制器，其被配置为使数据存储在第一存储器单元的存储器部分中，以使与数据相关联的纠错码的第一部分存储在第一存储器的另一个存储器部分中 并且使第二部分的纠错码存储在第二存储器单元中。 描述包括附加装置和方法的其他实施例。
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公开(公告)号：US08943387B2
公开(公告)日：2015-01-27
申请号：US13904331
申请日：2013-05-29
Applicant: Micron Technology, Inc.
Inventor： Michael Murray , William Henry Radke
CPC classification number: G06F11/1008 , G06F11/1072 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C29/00 , G11C2211/5642
Abstract: Methods, apparatus, systems, and data structures may operate to combine block management data with a portion of data, to generate error correction data for the combined portion, and to store the data, the block management data, the error correction data for the combined portion, and error correction data for the data in a memory. Additional embodiments may operate to generate or store error correction data for each of a plurality of sectors of a page except for a particular sector in the page and combine block management data with the particular sector to generate a modified sector. Additional embodiments may operate to generate or store error correction data for the modified sector and combine the plurality of sectors, the error correction data for each of the plurality of sectors other than the particular page, and the block management data and the error correction data for the modified sector.
Abstract translation: 方法，装置，系统和数据结构可以操作以将块管理数据与数据的一部分组合，以产生组合部分的纠错数据，并存储数据，块管理数据，组合的纠错数据 部分和用于存储器中的数据的纠错数据。 另外的实施例可以操作以生成或存储除了页面中的特定扇区之外的页面的多个扇区中的每一个的纠错数据，并且将块管理数据与特定扇区组合以生成修改的扇区。 另外的实施例可以操作以产生或存储修改的扇区的纠错数据，并组合多个扇区，除了特定页面之外的多个扇区中的每一个的纠错数据以及块管理数据和用于 修改部门。
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公开(公告)号：US08670272B2
公开(公告)日：2014-03-11
申请号：US13686488
申请日：2012-11-27
Applicant: Micron Technology, Inc.
Inventor： William Henry Radke
CPC classification number: G11C16/26 , G11C7/1021 , G11C16/04 , G11C16/3418 , G11C29/025 , G11C29/44 , G11C29/50
Abstract: A memory device is described that provides increased output data to help evaluate data errors from bit line coupling and floating gate coupling during a read operation. Multiple rows, or pages, of data are read to allow an internal or external decoder to evaluate memory cell data.
Abstract translation: 描述了一种存储器件，其提供增加的输出数据以帮助在读取操作期间从位线耦合和浮动栅极耦合评估数据错误。 读取多行或多页数据以允许内部或外部解码器评估存储器单元数据。
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