公开(公告)号：US5574729A

公开(公告)日：1996-11-12

申请号：US338817

申请日：1994-11-10

申请人： Mitsuya Kinoshita ,  Shigeru Mori ,  Yoshikazu Morooka ,  Hiroshi Miyamoto ,  Shigeru Kikuda ,  Makoto Suwa

发明人： Mitsuya Kinoshita ,  Shigeru Mori ,  Yoshikazu Morooka ,  Hiroshi Miyamoto ,  Shigeru Kikuda ,  Makoto Suwa

IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G06F11/00

CPC分类号： G11C29/848

摘要： A semiconductor memory device includes a plurality of memory blocks, i main row or column select lines extending over the plurality of memory blocks, and a decoder for selecting one of the main row or column select lines in accordance with an applied address signal. The decoder includes i outputs. Each of the memory blocks includes a plurality of memory cells arranged in rows and columns and at least (i+1) sub row or column select lines each for selecting one row or one column of memory cells. A shift redundancy circuit is provided for each of the memory blocks, for connecting the main row or column select line and the sub row or column select line. The shift redundancy circuit includes a switch circuit for connecting one main row or column select line to one of the plurality of adjacent sub row or column select lines, and a circuit for setting a connection path of the switch circuit. The shift redundancy circuit connects successively adjacent sub row or column select lines to main row or column select lines in one to one correspondence except a defective sub row or column select line associated with a defective bit.

摘要翻译： 一种半导体存储器件包括多个存储块，i个在多个存储块上延伸的主行或列选择线，以及用于根据所施加的地址信号选择主行或列选择线中的一个的解码器。 解码器包括i个输出。 每个存储块包括排列成行和列的多个存储器单元和至少（i + 1）个子行或列选择线，每个用于选择一行或一列存储单元。 为每个存储块提供移位冗余电路，用于连接主行或列选择线和子行或列选择线。 移位冗余电路包括用于将一个主行或列选择线连接到多个相邻子行或列选择线中的一个的开关电路和用于设置开关电路的连接路径的电路。 除了与有缺陷的位相关联的有缺陷的子行或列选择线之外，移位冗余电路将连续相邻的子行或列选择线以一对一的对应方式连接到主行或列选择线。

公开(公告)号：US5448512A

公开(公告)日：1995-09-05

申请号：US44676

申请日：1993-04-09

申请人： Atsushi Hachisuka ,  Kazuhiro Tsukamoto ,  Mitsuya Kinoshita

发明人： Atsushi Hachisuka ,  Kazuhiro Tsukamoto ,  Mitsuya Kinoshita

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  G11C11/401

CPC分类号： H01L27/10817

摘要： A portion of a cell plate 91 extending upon a field oxide film 107a and a silicon oxide film 123 is referred to as a lower layer interconnection film 109. The lower layer interconnection film 109 has a concave shape. A through hole 95a is formed in a silicon oxide film 93 reaching the bottom of the concave shape lower layer interconnection film 109. The depth of the through hole 95a is greater in comparison with the case where a through hole is formed on an upper face portion 123a of the silicon oxide film 123. Because the depth of through hole 95a is great, the thickness of the tungsten film 101a formed in through hole 95a becomes thicker. This eliminates the problem that all the tungsten film 101a in the through hole 95a, and then a portion of the lower layer interconnection film 109 are overetched. Therefore, electrical connection between the upper layer interconnection layer 103a and the lower layer interconnection layer 109 can be ensured.

摘要翻译： 在场氧化膜107a和氧化硅膜123上延伸的单元板91的一部分被称为下层互连膜109.下层布线膜109具有凹形。 在到达凹形下层互连膜109的底部的氧化硅膜93中形成通孔95a。与在上表面部分形成通孔的情况相比，通孔95a的深度更大 123a。由于通孔95a的深度大，所以形成在通孔95a中的钨膜101a的厚度变厚。 这消除了通孔95a中的所有钨膜101a以及下层互连膜109的一部分被过蚀刻的问题。 因此，可以确保上层布线层103a和下层布线层109之间的电连接。

公开(公告)号：US06930950B2

公开(公告)日：2005-08-16

申请号：US10706964

申请日：2003-11-14

申请人： Mitsuya Kinoshita ,  Hideyuki Noda

发明人： Mitsuya Kinoshita ,  Hideyuki Noda

IPC分类号： G11C11/407 ,  G11C7/12 ,  G11C11/409 ,  G11C11/4094 ,  G11C8/00

CPC分类号： G11C11/4094 ,  G11C7/12 ,  G11C2207/005

摘要： An XOR gate receives an input from a pair of read data lines to output a self-precharge signal when there is an increased potential difference between the paired read data lines. Thus, immediately after the increased potential difference between the paired read data lines occurs upon issuance of a read command, a precharge operation is autonomically performed. Therefore, no external precharge command is necessary when the read command is issued and thus a higher-speed operation is easily achieved.

摘要翻译： 当成对的读取数据线之间存在增加的电位差​​时，XOR门从一对读取数据线接收输入以输出自我预充电信号。 因此，在发出读取命令之后立即发生配对读取数据线之间的增加的电位差​​之后，自动执行预充电操作。 因此，当发出读取命令时，不需要外部预充电命令，因此容易实现更高速度的操作。

公开(公告)号：US06586329B1

公开(公告)日：2003-07-01

申请号：US09544997

申请日：2000-04-06

申请人： Yoshinori Tanaka ,  Mitsuya Kinoshita ,  Shinya Watanabe ,  Tatsuo Kasaoka ,  Moriaki Akazawa ,  Toshiaki Ogawa

发明人： Yoshinori Tanaka ,  Mitsuya Kinoshita ,  Shinya Watanabe ,  Tatsuo Kasaoka ,  Moriaki Akazawa ,  Toshiaki Ogawa

IPC分类号： H01L21311

CPC分类号： H01L27/1085 ,  H01L21/76802 ,  H01L23/5226 ,  H01L27/10852 ,  H01L28/82 ,  H01L28/86 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

摘要： A contact hole having an opening diameter smaller than the minimum dimension that can be formed by photolithographic technique is formed. Using an interlayer insulating film 8 formed on a semiconductor substrate as an etching mask, etching is carried out halfway to form an opening 8a. The etching mask is removed, and a TEOS film 10 is formed on the interlayer oxide film 8. The whole surface is then etched anisotropically to form a contact hole 11.

摘要翻译： 形成开口直径小于可通过光刻技术形成的最小尺寸的接触孔。 使用形成在半导体衬底上的层间绝缘膜8作为蚀刻掩模，进行中间蚀刻以形成开口8a。 除去蚀刻掩模，并在层间氧化膜8上形成TEOS膜10.然后，各向异性地蚀刻整个表面以形成接触孔11。

公开(公告)号：US5384784A

公开(公告)日：1995-01-24

申请号：US750040

申请日：1991-08-27

申请人： Shigeru Mori ,  Makoto Suwa ,  Hiroshi Miyamoto ,  Yoshikazu Morooka ,  Shigeru Kikuda ,  Mitsuya Kinoshita

发明人： Shigeru Mori ,  Makoto Suwa ,  Hiroshi Miyamoto ,  Yoshikazu Morooka ,  Shigeru Kikuda ,  Mitsuya Kinoshita

IPC分类号： G11C11/409 ,  G11C11/401 ,  G11C29/00 ,  G11C29/34 ,  G06F15/20

CPC分类号： G11C29/34

摘要： A semiconductor memory device includes a memory array. The bit line pairs of the odd number order in the memory array belong to a first group, and the bit line pairs of the even number order belong to a second group. A first amplifier is connected to each bit line pair. Corresponding to the first group, write buses read buses and a read/test circuit are provided. Corresponding to the second group, write buses read buses and a read/test circuit are provided. A column decoder selects a plurality of bit line pairs simultaneously at the time of testing. At the time of testing, each of the read/test circuits compares data read out from the plurality of bit line pairs belonging to the corresponding group with a given expected data for providing the comparison result.

摘要翻译： 半导体存储器件包括存储器阵列。 存储器阵列中奇数次序的位线对属于第一组，偶数顺序的位线对属于第二组。 第一放大器连接到每个位线对。 对应于第一组，写总线读总线和读/测电路。 对应于第二组，写总线读总线和读/测电路。 列解码器在测试时同时选择多个位线对。 在测试时，每个读/测试电路将从属于相应组的多个位线对中读出的数据与给定的预期数据进行比较，以提供比较结果。

公开(公告)号：US5223735A

公开(公告)日：1993-06-29

申请号：US915384

申请日：1992-07-20

申请人： Mitsuya Kinoshita ,  Kazutami Arimoto ,  Kiyohiro Furutani

发明人： Mitsuya Kinoshita ,  Kazutami Arimoto ,  Kiyohiro Furutani

IPC分类号： H01L21/768 ,  H01L23/525 ,  H01L27/118

CPC分类号： H01L21/76894 ,  H01L23/5258 ,  H01L27/118 ,  H01L2924/0002

摘要： A semiconductor integrated circuit device in which circuit functions can be remedied or changed by severing at least a portion of a circuit pattern and a method for producting such semiconductor integrated circuit device. The circuit pattern is formed on the semiconductor substrate. A field shield plate is formed on the major surface of the semiconductor substrate for electrically separating respective elements constituting the circuit. The circuit pattern includes a fuse element. The fuse element is provided on the field shield plate. The portion of the field shield plate lying directly below the fuse element is isolated from other portions of the field shield plate. In such semiconductor integrated circuit device, the portion of the field shield plate lying directly below the fuse element is separated from other portions of the field shield plate, so that short-circuiting between the semiconductor substrate and the field shield plate cannot occur even when the laser beam is irradiated with a laser beam deviation at the time of severing of the fuse element.

摘要翻译： 一种半导体集成电路器件，其中可以通过切断电路图案的至少一部分来补救或改变电路功能，以及用于产生这种半导体集成电路器件的方法。 电路图案形成在半导体衬底上。 在半导体基板的主表面上形成场屏蔽板，用于电分离构成电路的各个元件。 电路图案包括熔丝元件。 保险丝元件设置在场屏蔽板上。 位于保险丝元件正下方的场屏蔽板的部分与场屏蔽板的其它部分隔离。 在这样的半导体集成电路器件中，位于熔丝元件正下方的场屏蔽板的部分与场屏蔽板的其他部分分离，使得半导体衬底和场屏蔽板之间的短路即使在 激光束在熔断元件断开时被激光束的偏离照射。

公开(公告)号：US4974053A

公开(公告)日：1990-11-27

申请号：US331358

申请日：1989-03-31

申请人： Mitsuya Kinoshita ,  Tadato Yamagata ,  Hiroshi Miyamoto

发明人： Mitsuya Kinoshita ,  Tadato Yamagata ,  Hiroshi Miyamoto

IPC分类号： H01L21/60 ,  H01L23/485 ,  H01L23/495 ,  H01L23/498 ,  H01L23/50

CPC分类号： H01L24/49 ,  H01L23/49541 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/05 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/45124 ,  H01L2224/48247 ,  H01L2224/48699 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/30105

摘要： A semiconductor device having a bonding pad arrangement adaptable both to a package specification which requires lead terminals only along one longitudinal side of the package and to a specification which requires lead terminals to be arranged on both longitudinal sides of the package. The semiconductor device has a semiconductor substrate, a circuit formed on the semiconductor substrate, first and second groups of bonding pads respectively arranged along a first pair of two opposing sides of the semiconductor substrate, and third and fourth groups of bonding pads respectively arranged along a second pair of two opposing sides of the semiconductor substrate, the bonding pads of the first group being electrically connected to the circuit, each of the bonding pads of the third and fourth groups being employed for the same signal as a corresponding bonding pad of the second group, the bonding pads of the second group and the bonding pads of the third and fourth groups being selectively connectable to the circuit electrically.

摘要翻译： 一种具有焊盘布置的半导体器件，其适用于仅沿着封装的一个纵向侧面需要引线端子的封装规格以及需要将引线端子布置在封装的两个纵向侧面上的规格。 半导体器件具有半导体衬底，形成在半导体衬底上的电路，分别沿着半导体衬底的第一对相对侧布置的第一组焊盘和第二组焊盘，以及分别沿着半导体衬底 半导体衬底的第二对两个相对侧，第一组的焊盘电连接到电路，第三组和第四组的每个焊盘用于与第二组的相应的焊盘相同的信号 组，第二组的焊盘和第三和第四组的焊盘可电连接到电路。

公开(公告)号：US06272034B1

公开(公告)日：2001-08-07

申请号：US09606402

申请日：2000-06-29

申请人： Mitsuya Kinoshita ,  Fukashi Morishita ,  Kazutami Arimoto ,  Takeshi Fujino ,  Tetsushi Tanizaki ,  Takahiro Tsuruda ,  Teruhiko Amano ,  Mako Kobayashi

发明人： Mitsuya Kinoshita ,  Fukashi Morishita ,  Kazutami Arimoto ,  Takeshi Fujino ,  Tetsushi Tanizaki ,  Takahiro Tsuruda ,  Teruhiko Amano ,  Mako Kobayashi

IPC分类号： G11C502

CPC分类号： G11C5/025

摘要： A control circuit portion which controls the operations of memory cells is concentrated in a central portion and heat radiation plates are placed thereon via adhesive. A semiconductor integrated circuit having a function of the MPU or the like is placed above the control circuit portion via a bump electrode. The control circuit portion and a memory block are formed on separate chips respectively.

摘要翻译： 控制存储器单元的操作的控制电路部分集中在中心部分，并且热辐射板通过粘合剂放置在其上。 具有MPU等的功能的半导体集成电路经由凸块电极放置在控制电路部分上方。 控制电路部分和存储块分别形成在分开的芯片上。

公开(公告)号：US5892702A

公开(公告)日：1999-04-06

申请号：US710901

申请日：1996-09-24

申请人： Tatsuo Okamoto ,  Atsushi Hachisuka ,  Hideaki Arima ,  Mitsuya Kinoshita

发明人： Tatsuo Okamoto ,  Atsushi Hachisuka ,  Hideaki Arima ,  Mitsuya Kinoshita

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  G11C11/24

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： In a semiconductor memory device having cylindrical capacitors, word lines and a bit line are formed on a semiconductor substrate. A cylindrical storage node is connected to a conductive layer. The cylindrical storage node is provided at its inner wall with protruded conductive conductors which protrudes in a radially inward direction of the cylindrical storage node. A surface of the cylindrical storage node is covered with a capacitor insulating film. The outer surface of the cylindrical storage node is covered with a cell plate with the capacitor insulating film therebetween.

摘要翻译： 在具有圆柱形电容器的半导体存储器件中，在半导体衬底上形成字线和位线。 圆柱形存储节点连接到导电层。 圆柱形存储节点在其内壁处设置有突出的导电导体，其在圆柱形存储节点的径向向内的方向上突出。 圆柱形存储节点的表面被电容器绝缘膜覆盖。 圆柱形存储节点的外表面被其间具有电容器绝缘膜的单元板覆盖。

公开(公告)号：US5506164A

公开(公告)日：1996-04-09

申请号：US380181

申请日：1995-01-30

申请人： Mitsuya Kinoshita ,  Tatsuo Okamoto ,  Hideaki Arima ,  Atsushi Hachisuka

发明人： Mitsuya Kinoshita ,  Tatsuo Okamoto ,  Hideaki Arima ,  Atsushi Hachisuka

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： The semiconductor memory device includes a semiconductor substrate 1 having a conductive layer 6 formed on its main surface. Word lines 4c, 4d and a bit line 11 is formed on the semiconductor substrate. Insulating films 8, 12 are provided to cover the word lines 4c, 4d and the bit line 11. A barrier film 14 is provided on the insulating films 8, 12 for protecting the insulating films 8, 12 from etchant. A cylindrical storage node 170 is electrically connected to the conductive layer 6. The cylindrical storage node 170 includes a bottom conductive portion 17a and a sidewall conductive portion 17b. An outer surface of the storage node 170 is covered with a capacitor insulating film 112. The outer surface of the cylindrical storage node 170 is covered with a cell plate 22, with the capacitor insulating film 112 interposed therebetween.

摘要翻译： 半导体存储器件包括在其主表面上形成有导电层6的半导体衬底1。 字线4c，4d和位线11形成在半导体衬底上。 提供绝缘膜8,12以覆盖字线4c，4d和位线11.隔离膜14设置在绝缘膜8,12上，用于保护绝缘膜8,12免受蚀刻。 圆柱形存储节点170电连接到导电层6.圆柱形存储节点170包括底部导电部分17a和侧壁导电部分17b。 存储节点170的外表面被电容器绝缘膜112覆盖。圆筒形存储节点170的外表面被电池板22覆盖，电容器绝缘膜112插入其间。