公开(公告)号：US20180157779A1

公开(公告)日：2018-06-07

申请号：US15576947

申请日：2016-05-23

Applicant: NEC Corporation

Inventor： Noboru SAKIMURA ,  Yukihide TSUJI ,  Ayuka TADA ,  Xu BAI ,  Makoto MIYAMURA ,  Ryusuke NEBASHI

IPC: G06F17/50 ,  H03K19/003 ,  G11C7/22

Abstract: Provided is a programmable logic integrated circuit wherein even if a failure occurs in any resistance-variable element, remedy would be possible and hence the improvement of reliability has been achieved. In a programmable logic integrated circuit comprising resistance-variable elements, when the states of the resistance-variable elements are to be changed according to externally inputted configuration information, a control means uses a reading means to read the states of the respective resistance-variable elements, and then uses a writing means to change only the states of resistance-changing elements that are different from a state indicated by the configuration information.

公开(公告)号：US20170249981A1

公开(公告)日：2017-08-31

申请号：US15519851

申请日：2015-08-31

Applicant: NEC Corporation ,  TOHOKU UNIVERSITY

Inventor： Ryusuke NEBASHI ,  Noboru SAKIMURA ,  Yukihide TSUJI ,  Ayuka TADA ,  Hideo OHNO

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/08 ,  G11C11/15 ,  H01L27/105 ,  H01L29/82

CPC classification number: G11C11/16 ,  G11C11/15 ,  G11C11/1675 ,  H01L27/105 ,  H01L27/222 ,  H01L29/82 ,  H01L43/08

Abstract: In order to stably write data into a magnetic memory that uses in-plane current-induced perpendicular switching of magnetization to write data, the magnetic memory includes a recording layer formed as a perpendicular magnetization film, an adjacent layer joined to an upper surface or a lower surface of the recording layer, an external magnetic field application part configured to apply a first external magnetic field to the recording layer in a first direction which is an in-plane direction of the recording layer, and a current application part configured to allow a write current to flow through the adjacent layer in the first direction or a second direction which is opposite to the first direction. The external magnetic field application part is configured to switch a direction of a second external magnetic field applied in a direction perpendicular to the first direction in accordance with a direction of the write current.

公开(公告)号：US20210201996A1

公开(公告)日：2021-07-01

申请号：US16756554

申请日：2018-10-23

Applicant: NEC Corporation

Inventor： Toshitsugu SAKAMOTO ,  Naoki BANNO ,  Munehiro TADA ,  Yukihide TSUJI

IPC: G11C13/00 ,  H01L27/24

Abstract: Provided are a rewrite method for a variable resistance element that increases a rewrite count, and a non-volatile storage device using the variable resistance element. In the rewrite method for the variable resistance element, a variable resistance layer is disposed between a first electrode and a second electrode, and a write voltage is applied between the first electrode and the second electrode, thereby causing the resistance between the first electrode and the second electrode to reversibly change. After writing to the variable resistance element, the variable resistance element is read, the read current is measured, the measured read current is compared with a reference current, a condition of the writing is changed on the basis of the comparison results, and thereafter writing to the variable resistance element is performed again.

公开(公告)号：US20200266822A1

公开(公告)日：2020-08-20

申请号：US16648820

申请日：2018-09-14

Applicant: NEC Corporation

Inventor： Yukihide TSUJI ,  Toshitsugu SAKAMOTO ,  Makoto MIYAMURA ,  Ryusuke NEBASHI ,  Ayuka TADA ,  Xu BAI

IPC: H03K19/185 ,  H03K19/173 ,  H03K19/17704 ,  G11C13/00 ,  H01L27/24 ,  H01L45/00 ,  H03K19/17728 ,  H03K19/17756 ,  G06F7/57

Abstract: This logic integrated circuit has a plurality of first switch cells including variable resistance elements and a plurality of second switch cells including variable resistance elements. The logic integrated circuit comprises: a first output port and a second output port; the plurality of first switch cells for switching the electrical connections between a first wire and a third wire; the plurality of second switch cells for switching the electrical connections between a second wire and the third wire; a first control transistor which is connected to the first wire and which is for switching the electrical connections between the first wire and a first power line supplying power to the first wire; and a second control transistor which is connected to the second wire and which is for switching the electrical connections between the second wire and the first power line supplying power to the second wire.

公开(公告)号：US20200091914A1

公开(公告)日：2020-03-19

申请号：US16494419

申请日：2017-03-17

Applicant: NEC CORPORATION

Inventor： Xu BAI ,  Toshitsugu SAKAMOTO ,  Yukihide TSUJI ,  Makoto MIYAMURA ,  Ayuka TADA ,  Ryusuke NEBASHI

IPC: H03K19/173 ,  H03K19/177 ,  G06F21/76

Abstract: A reconfigurable circuit includes: a plurality of first lines; one or more second lines; a non-volatile resistive cell coupling one of the first lines with one of the second lines at each cross-point between the first lines and the second lines; and first switch elements including first terminals respectively coupled to the first lines, wherein each of the first switch elements is separately turned on or off in accordance with a control signal applied thereto.

公开(公告)号：US20190013811A1

公开(公告)日：2019-01-10

申请号：US16066738

申请日：2017-01-18

Applicant: NEC Corporation

Inventor： Yukihide TSUJI ,  Toshitsugu SAKAMOTO ,  Makoto MIYAMURA ,  Xu BAI ,  Ayuka TADA ,  Ryusuke NEBASHI

IPC: H03K19/177 ,  G11C13/00 ,  H01L27/24

Abstract: The purpose of the present invention is to increase the efficiency with which silicon on a chip is used, and to easily reduce the size of a logic cell. To accomplish the purpose, this reconfigurable circuit includes: a logic memory unit configured from a resistance change element, and positioned distributed into at least two units; a logic unit for referencing the logic memory unit and performing logical operations; and a signal path switching unit for receiving the results of the logical operation of the logic unit and outputting said results to the outside. The logic memory part and the signal path switching part constitute part of a crossbar switching circuit, and share write wiring to the resistance change element.

公开(公告)号：US20180096724A1

公开(公告)日：2018-04-05

申请号：US15550463

申请日：2016-03-01

Applicant: NEC Corporation

Inventor： Makoto MIYAMURA ,  Noboru SAKIMURA ,  Yukihide TSUJI ,  Ryusuke NEBASHI ,  Tadahiko SUGIBAYASHI

IPC: G11C13/00 ,  H01L27/24

CPC classification number: G11C13/004 ,  G06F7/00 ,  G06F7/544 ,  G11C13/0002 ,  G11C13/003 ,  G11C13/0064 ,  G11C13/0069 ,  G11C29/12015 ,  G11C29/50008 ,  G11C29/52 ,  G11C2013/0073 ,  G11C2029/5004 ,  G11C2213/75 ,  H01L27/2445 ,  H01L27/2481

Abstract: In order to provide a crossbar switch type memory circuit designed to be usable in normal circumstances even when a resistance change element is in an adverse state, the present invention is provided with: a first unit including a first column wiring to which one end of a first resistance change element is connected, a first power supply-side transistor for controlling the connection of the first column wiring and a power supply node, a first ground-side transistor, of a reverse operation type to the first power supply-side transistor, for controlling the connection of the first column wiring and a ground node, and a first polarity control line for causing the first power supply-side transistor or the first ground-side transistor to turn on and the other to turn off by a polar signal from a polar signal terminal, the first polarity control line being connected to the control terminals of the first power supply-side transistor and first ground-side transistor; a second unit including a second column wiring to which one end of a second resistance change element is connected, a second power supply-side transistor, of the same operation type as the first power supply-side transistor, for controlling the connection of the second column wiring and the power supply node, a second ground-side transistor, of a reverse operation type to the second power supply-side transistor, for controlling the connection of the second column wiring and the ground node, a logic inversion circuit for inverting the polarity of the polar signal from the polar signal terminal and outputting the polarity-inverted signal, and a second polarity control line for causing the second power supply-side transistor or the second ground-side transistor to turn on and the other to turn off by a polar signal from the logic inversion circuit, the second polarity control line being connected to the control terminals of the second power supply-side transistor and second ground-side transistor; and n row wirings (n: positive integer) to which the other ends of the first and second resistance change elements are connected.

公开(公告)号：US20210081591A1

公开(公告)日：2021-03-18

申请号：US17054653

申请日：2019-05-14

Applicant: NEC Corporation

Inventor： Ayuka TADA ,  Toshitsugu SAKAMOTO ,  Makoto MIYAMURA ,  Yukihide TSUJI ,  Ryusuke NEBASHI ,  Xu BAI

IPC: G06F30/3315

Abstract: A numerical information generating apparatus receives information of a programmable logic integrated circuit that includes a plurality of crossbar switches each including resistance change elements, calculates, for each of the plurality of crossbar switches, a base delay that is a delay in which influence of a load capacitance of other crossbar switch is excluded and a correction delay that is a delay caused by influence of a fanout of other crossbar switch, and further calculates a delay of each of the plurality of crossbar switches based on the base delay and the correction delay corresponding to each of the plurality of crossbar switches.

公开(公告)号：US20200380190A1

公开(公告)日：2020-12-03

申请号：US16766467

申请日：2018-11-21

Applicant: NEC Corporation

Inventor： Ryusuke NEBASHI ,  Toshitsugu SAKAMOTO ,  Makoto MIYAMURA ,  Yukihide TSUJI ,  Ayuka TADA ,  Xu BAI

IPC: G06F30/343 ,  G06F30/347

Abstract: A design assistance system including: a logic synthesis unit that receives input of an operation description file of the programmable logic integrated circuit, logically synthesizes the inputted operation description file, and generates a net list by using logic elements included in the programmable logic integrated circuit; an arrangement wiring unit that generates resource information of the programmable logic integrated circuit, arranges the logic elements included in the net list on the basis of the generated resource information, and virtually generates a signal path by laying wires among the arranged logic elements; and a reliability control unit that generates configuration information of the programmable logic integrated circuit on the basis of at least two reliability modes, and outputs the generated configuration information.

公开(公告)号：US20200336145A1

公开(公告)日：2020-10-22

申请号：US16957973

申请日：2019-01-21

Applicant: NEC Corporation

Inventor： Ryusuke NEBASHI ,  Toshitsugu SAKAMOTO ,  Makoto MIYAMURA ,  Yukihide TSUJI ,  Ayuka TADA ,  Xu BAI

IPC: H03K19/17736 ,  H03K19/17704 ,  H03K19/1776 ,  G11C13/00

Abstract: A logic integrated circuit includes a switch cell array. The switch cell array includes: a plurality of first wirings extending in a first direction; a plurality of second wirings extending in a second direction; a switch cell including a unit element including two serially connected resistance-changing elements, and a cell transistor to be connected to a shared terminal of the two resistance-changing elements; and a bit line to which the shared terminal is connected via the cell transistor. Two of the switch cells adjacent to each other in the first direction are each connected to the different first wiring and second wiring, and share the bit line, and a diffusion layer to which the bit line is connected.