公开(公告)号：US09390788B2

公开(公告)日：2016-07-12

申请号：US14809851

申请日：2015-07-27

Applicant: Nvidia Corporation

Inventor： Hwong-Kwo Lin ,  Lei Wang ,  Spencer Gold ,  Zhenye Jiang

IPC: G11C7/22 ,  G11C11/419 ,  G11C11/417 ,  G11C29/02 ,  G11C11/4076

CPC classification number: G11C11/419 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/417 ,  G11C29/022 ,  G11C29/028

Abstract: An SRAM clock circuit and an SRAM. In one embodiment, the SRAM clock circuit includes: (1) a plurality of transistor stacks optionally serially electrically couplable to form a configurable delay path through which a clock signal is buffered, and (2) a delay path select circuit respectively electrically coupled between pairs of the plurality of transistor stacks and operable to selectively electrically couple the plurality of transistor stacks to a base delay path, thereby activating the configurable delay path based on a desired delay.

Abstract translation: SRAM时钟电路和SRAM。 在一个实施例中，SRAM时钟电路包括：（1）多个晶体管堆叠，其可选地串联电耦合以形成缓冲时钟信号的可配置延迟路径;以及（2）延迟路径选择电路， 并且可操作以选择性地将多个晶体管堆叠电耦合到基本延迟路径，从而基于期望的延迟激活可配置的延迟路径。

公开(公告)号：US20150332757A1

公开(公告)日：2015-11-19

申请号：US14809851

申请日：2015-07-27

Applicant: Nvidia Corporation

Inventor： Hwong-Kwo Lin ,  Lei Wang ,  Spencer Gold ,  Zhenye Jiang

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/417 ,  G11C29/022 ,  G11C29/028

Abstract: An SRAM clock circuit and an SRAM. In one embodiment, the SRAM clock circuit includes: (1) a plurality of transistor stacks optionally serially electrically couplable to form a configurable delay path through which a clock signal is buffered, and (2) a delay path select circuit respectively electrically coupled between pairs of the plurality of transistor stacks and operable to selectively electrically couple the plurality of transistor stacks to a base delay path, thereby activating the configurable delay path based on a desired delay.

Abstract translation: SRAM时钟电路和SRAM。 在一个实施例中，SRAM时钟电路包括：（1）多个晶体管堆叠，其可选地串联电耦合以形成缓冲时钟信号的可配置延迟路径;以及（2）延迟路径选择电路， 并且可操作以选择性地将多个晶体管堆叠电耦合到基本延迟路径，从而基于期望的延迟激活可配置的延迟路径。

公开(公告)号：US20140125377A1

公开(公告)日：2014-05-08

申请号：US13668110

申请日：2012-11-02

Applicant: NVIDIA CORPORATION

Inventor： Hwong-Kwo Lin ,  Ge Yang ,  Xi Zhang ,  Jiani Yu ,  Ting-Hsiang Chu

IPC: H03K19/0175 ,  H03K19/00

CPC classification number: H03K3/356156 ,  G01R31/318541 ,  H03K3/356121

Abstract: A dual flip-flop circuit combines two or more flip-flip sub-circuits into a single circuit. The flip-flop circuit comprises a first flip-flop sub-circuit and a second flip-flop sub-circuit. The first flip-flop sub-circuit comprises a first storage sub-circuit configured to store a first selected input signal and transfer the first selected input signal to a first output signal when a buffered clock signal transitions between two different logic levels and a dock driver configured to receive a clock input signal, generate an inverted clock signal, and generate the buffered clock signal. The second flip-flop sub-circuit is coupled to the clock driver and configured to receive the inverted clock signal and the buffered clock signal. The second flip-flop sub-circuit comprises a second storage sub-circuit configured to store a second selected input signal and transfer the second selected input signal to a second output signal when the buffered clock signal transitions.

Abstract translation: 双触发器电路将两个或更多个触发器子电路组合成单个电路。 触发器电路包括第一触发器子电路和第二触发器子电路。 第一触发器子电路包括第一存储子电路，其被配置为存储第一选择的输入信号，并且当缓冲的时钟信号在两个不同逻辑电平之间转换时，将第一选定的输入信号传送到第一输出信号， 被配置为接收时钟输入信号，产生反相时钟信号，并产生缓冲的时钟信号。 第二触发器子电路耦合到时钟驱动器并且被配置为接收反相时钟信号和经缓冲的时钟信号。 第二触发器子电路包括第二存储子电路，其被配置为存储第二选择的输入信号，并且在缓冲的时钟信号转换时将第二选定的输入信号传送到第二输出信号。

公开(公告)号：US10181842B2

公开(公告)日：2019-01-15

申请号：US14945377

申请日：2015-11-18

Applicant: NVIDIA CORPORATION

Inventor： Ge Yang ,  Xi Zhang ,  Jiani Yu ,  Lingfei Deng ,  Hwong-Kwo Lin

IPC: H03K3/356 ,  H03K3/037

Abstract: A flip-flop element is configured to include FinFET technology transistors with a mix of threshold voltage levels. The data input path includes FinFET transistors configured with high voltage thresholds (HVT). The clock input path includes transistors configured with standard voltage thresholds (SVT). By including FinFET transistors with SVT thresholds in the clock signal path, the Miller capacitance of the clock signal path is reduced relative to HVT FinFET transistors, leading to lower rise time and correspondingly lower hold time. By including HVT threshold devices in the data input path, the flip-flop element attains high speed and low power operation. By including SVT threshold devices in the clock signal path, the flip-flop element achieves faster switching times in the clock signal path.

公开(公告)号：US09842631B2

公开(公告)日：2017-12-12

申请号：US13715991

申请日：2012-12-14

Applicant: NVIDIA Corporation

Inventor： Ge Yang ,  Hwong-Kwo Lin ,  Xi Zhang ,  Jiani Yu ,  Haiyan Gong

IPC: G11C7/12 ,  G11C11/4091

CPC classification number: G11C7/12 ,  G11C11/4091

Abstract: Mitigating external influences on long signal lines. In accordance with an embodiment of the present invention, a column of a memory array includes first and second transistors configured to pull up the bit line of the column. The column includes a third transistor configured to selectively pull up the bit line of the column responsive to a level of the inverted bit line of the column and a fourth transistor configured to selectively pull up the inverted bit line of the column responsive to a level of the bit line of the column. The column further includes fifth and sixth transistors configured to selectively pull up the bit line and inverted bit line of the column responsive to the clamp signal and a seventh transistor configured to selectively couple the bit line of the column and the inverted bit line of the column responsive to the clamp signal.

公开(公告)号：US20150235681A1

公开(公告)日：2015-08-20

申请号：US14279796

申请日：2014-05-16

Applicant: Nvidia Corporation

Inventor： Gang Chen ,  Jing Guo ,  Yiqi Wang ,  Hwong-Kwo Lin

IPC: G11C7/12

CPC classification number: G11C11/419 ,  G11C8/16 ,  G11C11/412

Abstract: A memory read system includes a memory column having a plurality of dual port memory cells that are controlled by separate read word lines and a read bit line structure organized into upper and lower read bit line portions. Additionally, the memory read system also includes a pseudo-differential memory read unit coupled to the read bit line structure, wherein the upper and lower read bit line portions respectively control corresponding upper and lower local bit lines to provide a global bit line for the memory column. A method of reading a memory is also included.

Abstract translation: 存储器读取系统包括具有多个双端口存储器单元的存储器列，该多个双端口存储器单元由分离的读取字线和被组织为上部和下部读取位线部分的读取位线结构控制。 此外，存储器读取系统还包括耦合到读取位线结构的伪差分存储器读取单元，其中上部和下部读取位线部分分别控制相应的上部和下部本地位线，以提供用于存储器的全局位线 柱。 还包括读取存储器的方法。

公开(公告)号：US20150222266A1

公开(公告)日：2015-08-06

申请号：US14170342

申请日：2014-01-31

Applicant: Nvidia Corporation

Inventor： Hwong-Kwo Lin ,  Ge Yang ,  Xi Zhang ,  Ying Huang

IPC: H03K19/003 ,  G06F1/10 ,  H03K3/037

CPC classification number: H03K19/003 ,  G06F1/10 ,  H03K3/0372

Abstract: A flip-flop and a method of receiving a digital signal from an asynchronous domain. In one embodiment, the flip-flop includes: (1) a first loop coupled to a flip-flop input and having first and second stable states and (2) a second loop coupled to the first loop and having the first and second stable states, properties of cross-coupled inverters in the first and second loops creating a metastable state skewed toward the first stable state in the first loop and skewed toward the second stable state in the second loop. Certain embodiments of the flip-flop have lower time constant and thus a higher Mean Time Between Failure (MTBF).

Abstract translation: 触发器和从异步域接收数字信号的方法。 在一个实施例中，触发器包括：（1）耦合到触发器输入并具有第一和第二稳定状态的第一环路和（2）耦合到第一环路并具有第一和第二稳定状态的第二环路 在第一和第二回路中的交叉耦合的反相器的特性产生亚稳态，其在第一回路中朝向第一稳定状态倾斜，并且朝向第二回路中的第二稳定状态倾斜。 触发器的某些实施例具有较低的时间常数，因此具有较高的平均故障间隔时间（MTBF）。

公开(公告)号：US20140169108A1

公开(公告)日：2014-06-19

申请号：US13715991

申请日：2012-12-14

Applicant: NVIDIA CORPORATION

Inventor： Ge Yang ,  Hwong-Kwo Lin ,  Xi Zhang ,  Jiani Yu ,  Haiyan Gong

IPC: G11C7/00

CPC classification number: G11C7/12 ,  G11C11/4091

Abstract: Mitigating external influences on long signal lines. In accordance with an embodiment of the present invention, a column of a memory array includes first and second transistors configured to pull up the bit line of the column. The column includes a third transistor configured to selectively pull up the bit line of the column responsive to a level of the inverted bit line of the column and a fourth transistor configured to selectively pull up the inverted bit line of the column responsive to a level of the bit line of the column. The column further includes fifth and sixth transistors configured to selectively pull up the bit line and inverted bit line of the column responsive to the clamp signal and a seventh transistor configured to selectively couple the bit line of the column and the inverted bit line of the column responsive to the clamp signal.

Abstract translation: 减轻对长信号线的外部影响。 根据本发明的实施例，存储阵列的列包括被配置为上拉列的位线的第一和第二晶体管。 该列包括第三晶体管，其被配置为响应于该列的反相位线的电平有选择地上拉该列的位线;以及第四晶体管，其被配置为响应于该列的反相位线选择性地上拉该反相位线 列的位线。 该列还包括第五和第六晶体管，其被配置为响应钳位信号选择性地上拉该列的位线和反相位线;以及第七晶体管，被配置为选择性地耦合该列的位线和该列的反相位线 响应钳位信号。

公开(公告)号：US20160269002A1

公开(公告)日：2016-09-15

申请号：US14644637

申请日：2015-03-11

Applicant: NVIDIA Corporation

Inventor： Xi Zhang ,  Hwong-Kwo Lin ,  Ge Yang ,  Lingfei Deng

IPC: H03K3/012 ,  H03K19/21 ,  H03K3/037

CPC classification number: H03K3/012 ,  G01R31/318541 ,  H03K3/0372 ,  H03K19/21

Abstract: Low clocking power flip-flop. In accordance with a first embodiment of the present invention, a flip-flop electronic circuit includes a master latch coupled to a slave latch in a flip-flop configuration. The flip-flop electronic circuit also includes a clock control circuit for comparing an input to the master latch with an output of the slave latch, and responsive to the comparing, blocking a clock signal to the master latch and the slave latch when the flip-flop electronic circuit is in a quiescent condition.

Abstract translation: 低时钟电源触发器。 根据本发明的第一实施例，触发器电子电路包括以触发器配置耦合到从锁存器的主锁存器。 触发器电子电路还包括用于将输入与主锁存器的输入与从锁存器的输出进行比较的时钟控制电路，并且响应于比较，当触发器电路电路将时钟信号阻塞到主锁存器和从锁存器时， 触发器电子电路处于静止状态。

公开(公告)号：US09219480B2

公开(公告)日：2015-12-22

申请号：US14170342

申请日：2014-01-31

Applicant: Nvidia Corporation

Inventor： Hwong-Kwo Lin ,  Ge Yang ,  Xi Zhang ,  Ying Huang

IPC: H03K3/00 ,  H03K19/003 ,  H03K3/037 ,  G06F1/10

CPC classification number: H03K19/003 ,  G06F1/10 ,  H03K3/0372

Abstract: A flip-flop and a method of receiving a digital signal from an asynchronous domain. In one embodiment, the flip-flop includes: (1) a first loop coupled to a flip-flop input and having first and second stable states and (2) a second loop coupled to the first loop and having the first and second stable states, properties of cross-coupled inverters in the first and second loops creating a metastable state skewed toward the first stable state in the first loop and skewed toward the second stable state in the second loop. Certain embodiments of the flip-flop have lower time constant and thus a higher Mean Time Between Failure (MTBF).

Abstract translation: 触发器和从异步域接收数字信号的方法。 在一个实施例中，触发器包括：（1）耦合到触发器输入并具有第一和第二稳定状态的第一环路和（2）耦合到第一环路并具有第一和第二稳定状态的第二环路 在第一和第二回路中的交叉耦合的反相器的特性产生亚稳态，其在第一回路中朝向第一稳定状态倾斜，并且朝向第二回路中的第二稳定状态倾斜。 触发器的某些实施例具有较低的时间常数，因此具有较高的平均故障间隔时间（MTBF）。