PROCESSING MODULE FOR A COMMUNICATION DEVICE AND METHOD THEREFOR

    公开(公告)号:US20190222443A1

    公开(公告)日:2019-07-18

    申请号:US16360945

    申请日:2019-03-21

    Applicant: NXP B.V.

    Abstract: A processing module for a receiver device. The processor module comprises a channel estimate generation component arranged to output channel estimate information for a received signal, and a timestamping module arranged to determine a ToA measurement for a marker within a packet of the received signal based at least partly on the channel estimate information for the received signal generated by the channel estimate generation component. The channel estimate generation component comprises a validation component arranged to derive a validation pattern for the packet within the received signal for which a ToA measurement is to be determined, identify a section of the packet containing a validation sequence, and perform cross-correlation between at least a part of the validation sequence within the packet and at least a part of the generated validation pattern to generate channel estimate validation information.

    Signal processing system and method

    公开(公告)号:US09916708B2

    公开(公告)日:2018-03-13

    申请号:US15605721

    申请日:2017-05-25

    Applicant: NXP B.V.

    Abstract: According to a first aspect of the present disclosure, a signal processing system is provided, comprising: a receiving unit configured to receive at least one signal that comprises a plurality of multipath components; a verification unit configured to correlate at least one multipath component under test with a reference signal derived from one or more of said plurality of multipath components. According to a second aspect of the present disclosure, a corresponding signal processing method is conceived. According to a third aspect of the present disclosure, a corresponding computer program is provided.

    Signal modulation for secure communication

    公开(公告)号:US09712496B2

    公开(公告)日:2017-07-18

    申请号:US14698226

    申请日:2015-04-28

    Applicant: NXP B.V.

    Abstract: Aspects of the present disclosure are directed to circuits, apparatuses and methods for generating communication signals resistant to early-detect-late-commit attacks. An example embodiment, a plurality of data symbols is generated that includes first and second data symbols. A communication signal is generated that is decodable according to a mapping of the first and second data symbols to respective first and second waveforms. The first waveform has a leading edge that is indicative of the first waveform, and second waveform has a second leading edge that is indicative of the second waveform. In generating the communication signal, a first portion of the communication signal is modulated according to the first waveform for the first data symbol. A second portion of the communication signal is modulated, for the second data symbol, according to a modified second waveform having a leading edge that is indicative of the first waveform.

    FREQUENCY SYNTHESIZERS WITH ADJUSTABLE DELAYS
    18.
    发明申请
    FREQUENCY SYNTHESIZERS WITH ADJUSTABLE DELAYS 有权
    具有可调延迟的频率合成器

    公开(公告)号:US20170063387A1

    公开(公告)日:2017-03-02

    申请号:US14836797

    申请日:2015-08-26

    Applicant: NXP B.V.

    Abstract: A radio frequency (RF) signal can be produced with an RF frequency that is responsive to a frequency reference (FREF) clock. An inductive-capacitive (LC) tank oscillator circuit can generate the RF signal. A digital to time converter (DTC) circuit can operate, for a first edge of the FREF clock, in a baseline mode that has a first delay, and for a subsequent edge of the FREF clock, in a delay mode that introduces a second delay value to the FREF clock. A controller circuit can enable the LC-tank oscillator circuit in response to a first edge of the FREF clock and to set or increase the second delay value of the delay mode as a function of the frequency of the RF signal. A phase detector circuit can detect, for the subsequent edge of the FREF clock, a phase difference between the FREF clock and the RF signal.

    Abstract translation: 射频(RF)信号可以产生具有响应于频率参考(FREF)时钟的RF频率。 电感电容(LC)振荡电路可以产生RF信号。 对于FREF时钟的第一边缘,数字到时间转换器(DTC)电路可以在具有第一延迟的基线模式中以及在FREF时钟的后续边沿处以引入第二延迟的延迟模式 值到FREF时钟。 控制器电路可以响应于FREF时钟的第一边缘而使LC-槽振荡器电路能够设置或增加作为RF信号的频率的函数的延迟模式的第二延迟值。 相位检测器电路可以检测FREF时钟的后续边沿FREF时钟和RF信号之间的相位差。

    Method and system for performing analog-to-digital conversion
    20.
    发明授权
    Method and system for performing analog-to-digital conversion 有权
    用于执行模数转换的方法和系统

    公开(公告)号:US09350375B1

    公开(公告)日:2016-05-24

    申请号:US14685501

    申请日:2015-04-13

    Applicant: NXP B.V.

    CPC classification number: H03M1/12 H03M1/1215 H03M1/1265

    Abstract: Methods and systems for performing analog-to-digital conversion are described. In one embodiment, a method for performing analog-to-digital conversion involves processing an analog impulse signal to obtain an impulse pattern of the analog impulse signal in a first signal processing path and converting the analog impulse signal into a digital signal based on the impulse pattern in a second signal processing path that is in parallel with the first signal processing path. The impulse pattern of the analog impulse signal includes duty cycle information of the analog impulse signal. Other embodiments are also described.

    Abstract translation: 描述用于执行模数转换的方法和系统。 在一个实施例中,用于执行模数转换的方法涉及处理模拟脉冲信号以在第一信号处理路径中获得模拟脉冲信号的脉冲模式,并且基于脉冲将模拟脉冲信号转换为数字信号 在与第一信号处理路径并联的第二信号处理路径中的图案。 模拟脉冲信号的脉冲模式包括模拟脉冲信号的占空比信息。 还描述了其它实施例。

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