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    CLOCK SELECTION CIRCUIT AND METHOD
    11.
    发明申请
    CLOCK SELECTION CIRCUIT AND METHOD 有权
    时钟选择电路和方法

    公开(公告)号：US20140223220A1

    公开(公告)日：2014-08-07

    申请号：US14175822

    申请日：2014-02-07

    Applicant: NXP B.V.

    Inventor： Surendra Guntur ,  Ghiath Al-kadi ,  Rinze Ida Mechtildis Peter Meijer ,  Jan Hoogerbrugge ,  Hamed Fatemi

    IPC: G06F1/08

    CPC classification number: G06F1/08 ,  G06F1/04 ,  G06F1/12

    Abstract: The invention provides a clock select circuit and method which uses feedback arrangements between latches in different branches, with each branch for coupling an associated clock signal to the circuit output. An override circuit is provided in one of the feedback arrangements for preventing a latching delay in that feedback arrangement. This enables rapid switching between clocks in both directions.

    Abstract translation: 本发明提供一种时钟选择电路和方法，其使用不同分支中的锁存器之间的反馈装置，每个分支用于将相关联的时钟信号耦合到电路输出。 在用于防止该反馈装置中的锁定延迟的反馈装置中的一个中提供了超控电路。 这使得能够在两个方向上的时钟之间快速切换。

    Apparatus for processing a signal
    12.
    发明授权
    Apparatus for processing a signal 有权

    公开(公告)号：US11461642B2

    公开(公告)日：2022-10-04

    申请号：US16566991

    申请日：2019-09-11

    Applicant: NXP B.V. ,  TECHNISCHE UNIVERSITEIT EINDHOVEN

    Inventor： Jose De Jesus Pineda de Gyvez ,  Hamed Fatemi ,  Emad Ayman Taleb Ibrahim

    IPC: G06N3/08 ,  G06N20/10 ,  G06F3/01 ,  G10L15/16

    Abstract: An apparatus for processing a signal for input to a neural network, the apparatus configured to: receive a signal comprising a plurality of samples of an analog signal over time; determine at least one frame comprising a group of consecutive samples of the signal, wherein the or each frame includes a first number of samples; for each frame, determine a set of correlation values comprising a second number of correlation values, the second number less than the first number, each correlation value of the set of correlation values based on an autocorrelation of the frame at a plurality of different time lags; provide an output based on the set of correlation values corresponding to the or each of the frames for a neural network for one or more of classification of the analog signal by the neural network and training the neural network based on a predetermined classification.

    Event-Based Power Manager
    13.
    发明申请
    Event-Based Power Manager 审中-公开

    公开(公告)号：US20190146566A1

    公开(公告)日：2019-05-16

    申请号：US15813861

    申请日：2017-11-15

    Applicant: NXP B.V.

    Inventor： Jose de Jesus Pineda de Gyvez ,  Hamed Fatemi ,  Manuele Rusci ,  Luca Benini ,  Elisabetta Farella ,  Davide Rossi

    IPC: G06F1/32 ,  G06F11/34 ,  G06F9/48

    Abstract: A technique for managing power in an embedded processing system includes generating a workload model for the embedded processing system in response to a control signal, an event status signal, and a reference clock signal. The control signal is received from a peripheral device. The event status signal is received from an event processor configured to control execution of tasks by a processor core of the embedded processing system. The technique includes providing power configuration information to the processor core. The power configuration information corresponds to an operating point selected based on the control signal, the event status signal, the reference clock signal, the workload model, and a predetermined energy model.

    Level shifter circuit with transistor drive strength variation compensation
    14.
    发明授权
    Level shifter circuit with transistor drive strength variation compensation 有权

    公开(公告)号：US10270448B1

    公开(公告)日：2019-04-23

    申请号：US15980882

    申请日：2018-05-16

    Applicant: NXP B.V.

    Inventor： Kristof Blutman ,  Sebastien Antonius Josephus Fabrie ,  Juan Diego Echeverri Escobar ,  Ajay Kapoor ,  Jose de Jesus Pineda de Gyvez ,  Hamed Fatemi

    IPC: H03K19/0185

    Abstract: A level shifter circuit is described herein for shifting a signal from a first voltage domain to a second voltage domain. The level shifter circuit includes two current paths between a supply terminal of the first voltage domain and a supply terminal of the second voltage domain. The first and second current paths each include a differential transistor that receives a signal from a pulse generator in a first voltage domain. The pulse generator provides pulses to the differential transistors based on an input signal to be translated to the second voltage domain. The level shifter includes a latch circuit in the second voltage domain that includes two inputs where each input is biased at a node of one of the current paths. Each current path includes a bias transistor whose control terminal receives a compensated biasing voltage for biasing the bias transistor. The compensated biasing voltage is compensated to account for drive strength variation of at least one transistor in each current path.

    Parallel execution of instructions in processing units and adjusting power mode based on monitored data dependency over a period of time
    15.
    发明授权
    Parallel execution of instructions in processing units and adjusting power mode based on monitored data dependency over a period of time 有权
    在处理单元中并行执行指令，并根据一段时间内监视的数据依赖性调整功耗模式

    公开(公告)号：US09465614B2

    公开(公告)日：2016-10-11

    申请号：US14195657

    申请日：2014-03-03

    Applicant: NXP B.V.

    Inventor： Hamed Fatemi ,  Jose Pineda de Gyvez ,  Juan Echeverri Escobar

    IPC: G06F9/30 ,  G06F1/32 ,  G06F9/38

    CPC classification number: G06F9/30145 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3287 ,  G06F1/329 ,  G06F1/3293 ,  G06F1/3296 ,  G06F9/30189 ,  G06F9/3836 ,  G06F9/3869 ,  G06F9/3885 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/24

    Abstract: An integrated circuit comprising a set of data processing units including a first data processing unit and at least one second data processing unit operable at variable frequencies is disclosed. The integrated circuit further includes an instruction scheduler adapted to evaluate data dependencies between individual instructions in a received plurality of instructions and assign the instructions to the first data processing unit and the at least one second data processing unit for parallel execution in accordance with said data dependencies. The integrated circuit is operable in a first power mode and a second power mode. The second power mode is a reduced power mode compared to the first power mode and is adapted to adjust the operating frequency of the first data processing unit and the at least one second data processing unit in the second power mode as a function of the evaluated data dependencies.

    Abstract translation: 一种集成电路，包括一组数据处理单元，包括第一数据处理单元和至少一个以可变频率工作的第二数据处理单元。 集成电路还包括指令调度器，其适于评估接收的多个指令中的各个指令之间的数据依赖性，并且将指令分配给第一数据处理单元和至少一个第二数据处理单元，用于根据所述数据依赖性进行并行执行 。 集成电路可在第一功率模式和第二功率模式下操作。 第二功率模式是与第一功率模式相比的降低功率模式，并且适于根据评估数据调整第二数据处理单元和第二功率模式中的至少一个第二数据处理单元的工作频率 依赖关系。

    Event-based power manager
    18.
    发明授权
    Event-based power manager 有权

    公开(公告)号：US10732698B2

    公开(公告)日：2020-08-04

    申请号：US15813861

    申请日：2017-11-15

    Applicant: NXP B.V.

    Inventor： Jose de Jesus Pineda de Gyvez ,  Hamed Fatemi ,  Manuele Rusci ,  Luca Benini ,  Elisabetta Farella ,  Davide Rossi

    IPC: G06F1/32 ,  G06F1/324 ,  G06F11/34 ,  G06F9/48 ,  G06F1/3228 ,  G06F1/329 ,  G06F1/3234

    Abstract: A technique for managing power in an embedded processing system includes generating a workload model for the embedded processing system in response to a control signal, an event status signal, and a reference clock signal. The control signal is received from a peripheral device. The event status signal is received from an event processor configured to control execution of tasks by a processor core of the embedded processing system. The technique includes providing power configuration information to the processor core. The power configuration information corresponds to an operating point selected based on the control signal, the event status signal, the reference clock signal, the workload model, and a predetermined energy model.

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