公开(公告)号：US20090316484A1

公开(公告)日：2009-12-24

申请号：US12095866

申请日：2006-12-01

申请人： Hiroshi Sunamura ,  Kouji Masuzaki ,  Masayuki Terai

发明人： Hiroshi Sunamura ,  Kouji Masuzaki ,  Masayuki Terai

IPC分类号： G11C16/04 ,  H01L29/792 ,  H01L21/336

CPC分类号： H01L21/28282 ,  G11C16/0466 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/792

摘要： Disclosed is a semiconductor storage device comprising a semiconductor substrate, a first and a second impurity diffusion layer formed in the semiconductor substrate, a gate insulating film formed on the semiconductor substrate, and a first gate electrode formed on the semiconductor substrate via the gate insulating film. The gate insulating film has a nitrogen-containing silicon oxide film inside, and a silicon oxide film is so arranged on both sides of the nitrogen-containing silicon oxide film as to sandwich the nitrogen-containing silicon oxide film. In addition, the nitrogen composition in the nitrogen-containing silicon oxide film is increased from the semiconductor substrate side to the first gate electrode side.

摘要翻译： 公开了一种半导体存储装置，包括半导体衬底，形成在半导体衬底中的第一和第二杂质扩散层，形成在半导体衬底上的栅极绝缘膜，以及通过栅极绝缘膜形成在半导体衬底上的第一栅电极 。 栅极绝缘膜在内部具有含氮氧化硅膜，并且在含氮氧化硅膜的两侧配置氧化硅膜以夹持含氮氧化硅膜。 此外，含氮氧化硅膜中的氮组成从半导体衬底侧增加到第一栅电极侧。

公开(公告)号：US09514807B2

公开(公告)日：2016-12-06

申请号：US14955789

申请日：2015-12-01

申请人： YounSeon Kang ,  Jungdal Choi ,  Masayuki Terai ,  Youngbae Kim ,  Jung Moo Lee ,  Seungjae Jung

发明人： YounSeon Kang ,  Jungdal Choi ,  Masayuki Terai ,  Youngbae Kim ,  Jung Moo Lee ,  Seungjae Jung

IPC分类号： G11C11/34 ,  G11C13/00 ,  G11C11/16 ,  G11C8/00 ,  G11C7/00

CPC分类号： G11C13/0004 ,  G11C7/00 ,  G11C8/00 ,  G11C11/16 ,  G11C11/1659 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/224 ,  H01L27/2409 ,  H01L27/2481

摘要： A variable resistance memory device includes upper interconnections on a substrate, first and second word lines provided between the substrate and the upper interconnections and vertically spaced apart from each other, a first bit line disposed between the first and second word lines and intersecting the first and second word lines, memory cells provided in an intersecting region of the first word line and the first bit line and an intersecting region of the second word line and the first bit line, a first word line contact directly connecting the first word line to a corresponding one of the upper interconnections, and a second word line contact directly connecting the second word line to a corresponding one of the upper interconnections.

摘要翻译： 可变电阻存储器件包括衬底上的上部互连，设置在衬底和上部互连之间并且彼此垂直间隔开的第一和第二字线，设置在第一和第二字线之间并与第一和第二字线相交的第一位线 第二字线，设置在第一字线和第一位线的交叉区域中的存储单元以及第二字线和第一位线的相交区域，将第一字线直接连接到相应的第一字线 上部互连中的一个，以及将第二字线直接连接到上部互连中的相应一个的第二字线接触。

公开(公告)号：US08300448B2

公开(公告)日：2012-10-30

申请号：US12922783

申请日：2009-03-24

申请人： Masayuki Terai

发明人： Masayuki Terai

IPC分类号： G11C27/00

CPC分类号： H01L27/101 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633 ,  H01L45/1675

摘要： A semiconductor storage device is provided for solving the problem of the inability to simultaneously realize high reliability and decreased cell area. A selection electrode (106) is formed to sandwich an insulating film (105) with a p-type semiconductor region (102). A first n-type semiconductor region (103) and a second n-type semiconductor region (104) are formed in the p-type semiconductor region (102) at two sides of the selection electrode (106). A first resistance-changing layer (107) is connected to the first n-type semiconductor region (103), and a second resistance-changing layer (109) is connected to the second n-type semiconductor region (104). In addition, a first wiring layer (108) is connected to the second resistance-changing layer (109), and a second wiring layer (110) is connected to the second resistance-changing layer (109).

摘要翻译： 提供半导体存储装置，用于解决不能同时实现高可靠性和减小单元面积的问题。 选择电极（106）被形成为用p型半导体区域（102）夹住绝缘膜（105）。 在选择电极（106）的两侧的p型半导体区域（102）中形成第一n型半导体区域（103）和第二n型半导体区域（104）。 第一电阻变化层（107）连接到第一n型半导体区域（103），第二电阻变化层（109）连接到第二n型半导体区域（104）。 此外，第一布线层（108）连接到第二电阻变化层（109），第二布线层（110）连接到第二电阻变化层（109）。

公开(公告)号：US20090201739A1

公开(公告)日：2009-08-13

申请号：US12304322

申请日：2007-04-24

申请人： Masayuki Terai

发明人： Masayuki Terai

IPC分类号： G11C16/06 ,  G11C11/34 ,  H01L29/792

CPC分类号： H01L27/11568 ,  G11C16/0466 ,  G11C16/10 ,  H01L27/115 ,  H01L29/42344 ,  H01L29/42348 ,  H01L29/66833 ,  H01L29/7923

摘要： In a case of writing to a trap type non-volatile memory cell that includes: a laminated insulating film, containing a charge accumulation layer, that is formed on a semiconductor substrate where source, drain and well regions are formed; and a first gate electrode formed on the laminated insulating film, charge injections that are carried on a single memory node multiple times under two or more different writing conditions, the writing condition is a combination of a well voltage applied to the well, a drain voltage applied to the drain and a gate voltage is applied to the first gate. Thereby, it is possible to form a trapezoid-shaped electron distribution in the charge accumulation layer, and thus prevent the charge retention characteristic from deteriorating.

摘要翻译： 在写入陷阱型非易失性存储单元的情况下，包括：形成在形成有源极，漏极和阱区的半导体衬底上的电荷累积层的层叠绝缘膜; 以及形成在层叠绝缘膜上的第一栅极电极，在两个以上不同的写入条件下多次承载在单个存储器节点上的电荷注入，写入条件是施加到阱的阱电压，漏极电压 施加到漏极，并且栅极电压被施加到第一栅极。 因此，可以在电荷累积层中形成梯形电子分布，从而防止电荷保持特性劣化。

公开(公告)号：US08902630B2

公开(公告)日：2014-12-02

申请号：US13553764

申请日：2012-07-19

申请人： Masaharu Matsudaira ,  Masayuki Terai

发明人： Masaharu Matsudaira ,  Masayuki Terai

IPC分类号： G11C11/00 ,  H01L27/108 ,  H01L45/00 ,  H01L27/24 ,  H01L49/02 ,  H01L27/105

摘要： In a case where a DRAM and a ReRAM are mounted together, a manufacturing cost thereof is reduced while maintaining performance of a capacitance element and a variable resistance element. A semiconductor memory device includes a variable resistance element and a capacitance element. The variable resistance element has a cylinder type MIM structure with a first depth, and is designed for a variable resistance type memory. The capacitance element has a cylinder type MIM structure with a second depth deeper than the first depth, and is designed for a DRAM.

公开(公告)号：US20120267598A1

公开(公告)日：2012-10-25

申请号：US13499956

申请日：2010-10-04

申请人： Yukihiro Sakotsubo ,  Masayuki Terai ,  Munehiro Tada ,  Yuko Yabe ,  Yukishige Saito

发明人： Yukihiro Sakotsubo ,  Masayuki Terai ,  Munehiro Tada ,  Yuko Yabe ,  Yukishige Saito

IPC分类号： H01L47/00 ,  H01L21/02

CPC分类号： H01L21/02186 ,  H01L21/02183 ,  H01L21/022 ,  H01L21/02244 ,  H01L21/02266 ,  H01L27/101 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1608

摘要： A semiconductor device includes at least first and second electrodes, and a layer including a transition metal oxide layer sandwiched between the first and second electrodes. The transition metal oxide layer includes first and second transition metal oxide layers formed of different first and second transition metals, respectively. The first transition metal oxide layer is provided on the first electrode side, the second transition metal oxide layer is provided on the second electrode side, the first transition metal oxide layer and the second transition metal oxide layer are in contact with each other, the first transition metal oxide layer has an oxygen concentration gradient from the interface between the first transition metal oxide layer and the second transition metal oxide layer toward the first electrode side, and the oxygen concentration at the interface is greater than the oxygen concentration on the first electrode side.

摘要翻译： 半导体器件至少包括第一和第二电极，以及包括夹在第一和第二电极之间的过渡金属氧化物层的层。 过渡金属氧化物层分别包括由不同的第一和第二过渡金属形成的第一和第二过渡金属氧化物层。 第一过渡金属氧化物层设置在第一电极侧，第二过渡金属氧化物层设置在第二电极侧，第一过渡金属氧化物层和第二过渡金属氧化物层彼此接触，第一过渡金属氧化物层 过渡金属氧化物层具有从第一过渡金属氧化物层和第二过渡金属氧化物层之间的界面朝向第一电极侧的氧浓度梯度，并且界面处的氧浓度大于第一电极侧的氧浓度 。

公开(公告)号：US08106444B2

公开(公告)日：2012-01-31

申请号：US12514647

申请日：2007-11-05

申请人： Masayuki Terai

发明人： Masayuki Terai

IPC分类号： H01L29/792 ,  H01L29/04

CPC分类号： H01L27/11565 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/7923

摘要： Provided is a semiconductor device including: source-drain regions formed on a silicon substrate with a channel forming region sandwiched therebetween; a word gate electrode formed on the channel forming region via a word gate insulating film not including a charge storage layer; a control gate formed on the silicon substrate on one side of the word gate electrode via a trap insulating film including a charge storage layer; and a control gate formed on the silicon substrate on the other side of the word gate electrode via a trap insulating film including a charge storage layer. A bottom of the word gate electrode is made to be higher than the control gate and a bottom of the control gate, and a level difference between the bottoms of the electrodes is made to be larger than a physical film thickness of the word gate insulating film.

摘要翻译： 提供一种半导体器件，包括：源极 - 漏极区，形成在硅衬底上，沟道形成区域夹在其间; 通过不包含电荷存储层的字栅绝缘膜形成在沟道形成区上的字栅电极; 通过包含电荷存储层的阱绝缘膜在所述字栅电极的一侧的所述硅衬底上形成的控制栅极; 以及通过包含电荷存储层的阱绝缘膜在所述字栅电极的另一侧的所述硅衬底上形成的控制栅极。 使字栅电极的底部高于控制栅极和控制栅极的底部，并且使电极的底部之间的电平差大于字栅绝缘膜的物理膜厚度 。

公开(公告)号：US20110096595A1

公开(公告)日：2011-04-28

申请号：US12999981

申请日：2009-06-19

申请人： Masayuki Terai

发明人： Masayuki Terai

IPC分类号： G11C11/56 ,  H01L45/00 ,  H01L21/02

CPC分类号： G11C13/0007 ,  H01L27/101 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1641

摘要： Disclosed is a resistance change type nonvolatile memory that has an insulation film structure, is advantageous for the implementation of high integration, and achieves a stable switching characteristic, and a manufacturing method therefor. The memory includes at least an MIM (Metal/Insulator/Metal) structure including an insulation film (2) sandwiched between metal electrodes (1) and (3), and the insulation film (2) includes a laminated structure including a Ta2O5 film and a TiO2 film with a thickness of less than 30 nm. The Ta2O5 film is a stoichiometric amorphous film.

摘要翻译： 公开了具有绝缘膜结构的电阻变化型非易失性存储器，有利于实现高集成度，并实现稳定的开关特性及其制造方法。 存储器至少包括夹在金属电极（1）和（3）之间的绝缘膜（2）的MIM（金属/绝缘体/金属）结构，绝缘膜（2）包括层叠结构，其包括Ta 2 O 5膜和 厚度小于30nm的TiO 2膜。 Ta2O5膜是化学计量的非晶膜。

公开(公告)号：US07791129B2

公开(公告)日：2010-09-07

申请号：US12162224

申请日：2007-01-18

申请人： Masayuki Terai

发明人： Masayuki Terai

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/115 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

摘要： There is provided a trap memory device suppresses electric charges from flowing from the outside into a charge accumulation region and accumulated electric charges from diffusing to the outside or flowing out due to a defect. A gate conductor 6 is formed through a laminate insulating film including a first gate insulating film 3, a charge accumulation layer 4 and a second gate insulating film 5 on a silicon substrate 1. The laminate insulating film (3 to 5) projects outside the gate conductor 6 and extends to under the outer end of a side wall 8. The charge accumulation layer 4 includes a high trap surface-density region 4a immediately under the gate conductor and a low trap surface-density region 4b outside the gate conductor.

摘要翻译： 提供了一种陷阱存储器件，其抑制电荷从外部流入电荷累积区域，并且积聚的电荷从扩散到外部或由于缺陷而流出。 栅极导体6通过在硅衬底1上包括第一栅极绝缘膜3，电荷累积层4和第二栅极绝缘膜5的层压绝缘膜形成。层叠绝缘膜（3至5）突出于栅极外部 导体6并延伸到侧壁8的外端。电荷累积层4包括位于栅极导体正下方的高陷阱表面密度区域4a和位于栅极导体外部的低陷阱表面密度区域4b。

公开(公告)号：US4835705A

公开(公告)日：1989-05-30

申请号：US014374

申请日：1987-02-10

申请人： Yasuhiro Fujino ,  Masayuki Terai ,  Tomoyoshi Noda ,  Yoshihide Ajioka

发明人： Yasuhiro Fujino ,  Masayuki Terai ,  Tomoyoshi Noda ,  Yoshihide Ajioka

IPC分类号： H01L21/3205 ,  G06F17/50 ,  H01L21/82 ,  H01L23/52 ,  H01L27/118

CPC分类号： G06F17/5077

摘要： The present invention provides an interconnection area decision processor for deciding vertical widths of areas employed for interconnection of a gate array. The interconnection area decision processor predicts which interconnection area each signal net passes on the basis of previously created data on cell arrangement and data on arrangement of transistor rows on a chip to estimate interconnection congestion per channel on the basis of the result of prediction and decide the number of transistor rows to be assigned to each channel on the basis of the estimated interconnection congestion, thereby to create data on the vertical width of each channel. Thus, density of integration can be improved by increasing the number of tracks of channels having large numbers of interconnections and decreasing the number of tracks of channels having small numbers of interconnections.

摘要翻译： 本发明提供了一种用于确定用于门阵列互连的区域的垂直宽度的互连区决定处理器。 互连区域判定处理器根据先前创建的关于单元布置的数据和芯片上的晶体管行的布置数据来预测每个信号网络哪个互连区域通过哪个互连区域，以基于预测结果估计每个信道的互连拥塞，并且决定 基于估计的互连拥塞来分配给每个信道的晶体管行数，从而在每个通道的垂直宽度上创建数据。 因此，通过增加具有大量互连的通道的轨道数量并减少具有少量互连的通道的轨道数量，可以提高积分密度。